RECEIVE
OUR
UPDATED
BOUNDARY
SCAN
TUTORIAL
HANDBOOK
2007

ASSET's leadership position in the boundary-scan/JTAG industry began with its participation in the development of the IEEE 1149.1 standard in the mid-1990s. Since then, the company has consistently been at the forefront of research and development. Over the years, a number of ASSET developments were truly pioneering efforts. For example, ASSET’s boundary-scan test and in-system programming system, ScanWorks, can be traced back to the first commercially available JTAG system. Back then, it was simply called the ASSET system. Now, another of our breakthrough products, DFT Analyzer, is the industry’s only automatic JTAG design-for-test tool. In addition, ScanWorks was the first tool to offer IEEE 1149.6 testing of high-speed differential and AC-coupled buses, and it was the first JTAG system to support the embedded Intel® Interconnect Built In Self Test (IBIST) technology. We also pioneered the concept of free online libraries of resources like our cluster model and scripting libraries.

Distinct from our technology leadership, we believe in giving back to the industry. ASSET personnel have either led or participated in numerous standards development efforts. In fact, ASSET is responsible for maintaining the industry standard for Serial Vector Format (SVF). With Agilent Technologies, we co-developed and are currently hosting a free BSDL validation service. The other standards development efforts we’ve participated in are PICMG's MicroTCA specification, the IEEE P1687 Internal JTAG (IJTAG) effort, the ad hoc System JTAG working group, the IEEE 1532 standard for concurrent in-system program and JEDEC's STAPL standard.

Technical Resources

In general, the ASSET web site features a wealth of pertinent information on JTAG and boundary-scan technologies, design-for-test and other topics. Take a look at the list below and click on what interests you. It’s all free and immediately accessible.

• Boundary Scan Tutorial, a 110-page primer on the technology
• Guidelines for Device DFT Based on Boundary Scan
• Guidelines for Board DFT Based on JTAG/Boundary Scan:
•            Board DFT Guidelines - Part 1
•            Board DFT Guidelines - Part 2
• Guidelines for Chip & Board Testability Assessment Checklist:
• Chip & Board Testability Assessment Checklist
• 10 Hot Issues When Considering Buying Your Boundary-Scan Toolset”
• Design Rules for designing boundary scan into your device, board, or system
• SVF Specification (Serial Vector Format)
• HSDL Specification (Hierarchical Scan Description Language)
• DFT Analyzer ROI Calculator

ASSET Speaks Out

Glenn Woppman's guest commentary in Test and Measurement World Magazine, “"Investments in JTAG standards development benefits entire industry"”

Glenn Woppman shares his views on the future of boundary-scan technology in an interview with Test and Measurement World Magazine.
           Part 1 of the Interview.
           Part 2 of the Interview.

Glenn Woppman discusses the new IJTAG and SJTAG initiatives.

For some of the recent articles ASSET executives have contributed to leading
publications in the test industry, click here.

Our Connect e-newsletter is also a great source for boundary-scan information.
Click here to see the archive of past issues and articles and subscribe to future issues.

To speak with an ASSET representative, click here.