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ScanWorks steps up to signal integrity issues
You won’t hear signal integrity engineers spouting that old saying, “ignorance is bliss.” Their job is to dispel ignorance. It’s just that the industry has been conspiring against them lately, placing perplexing obstacles in their way. Now though, new tools are emerging that give greater visibility to signal integrity issues. Soon, perhaps, signal integrity engineers might just start feeling a bit more blissful.
Between the transmitter and receiver, a digital communications signal can fall prey to any number of factors that degrade its strength and integrity. Crosstalk from adjacent channels can bleed over into the channel in question and interfere with the signals. When signals surpass 1 GHz, dielectric loss and ‘skin effect’ contribute to significant signal loss. As today’s buses start pushing 10 gigabits per second (Gbps), these losses can add up quickly. Inter-symbol interference (ISI) can also occur. This arises when a bit interferes with its neighboring bits. Impedance mismatches, which cause reflections in a communications cannel, can also be a problem.
Measuring Integrity
A signal integrity analysis on a circuit board or system these days begins with determining how and where it can be measured, which is no mean feat in its own right. The good old days of placing an oscilloscope probe on a test pad or on a device pin are quickly fading into a not too distant past.
The new day dawning involves high-speed serial buses rather than the slower parallel buses. Unfortunately, placing that probe on a high-speed serial bus introduces capacitance onto the bus, corrupting the integrity of the signals to the point where a measurement of signal integrity is no longer valid. But, of course, this assumes that the engineer can even find a pad or a pin where the probe can be placed. Device packages like ball grid arrays (BGA), multi-layer circuit boards, and new types of packaging involving multi-core devices in system-in-package (SiP), package-on-package (PoP) and others are hastening the disappearance of the usual probing locations. As a result, more and more engineers are considering embedded instrumentation to measure the integrity of signals and they may soon be turning to tools like ScanWorks to access embedded instruments, automate their execution and analyze the results they generate.
Getting a Fix on Signal Integrity
Generally speaking, bit error rates are used to specify an acceptable level of signal integrity. Then, bit error rate testing (BERT) is performed to determine the actual integrity of a communications channel. Other performance parameters relate to signal integrity as well. These include the opening in an eye diagram, edge speeds of a digital signal, and power or voltage levels.
Exacerbating how difficult it can be to measure signal integrity is the fact that for high-speed serial buses the channel’s timing clock is embedded with the data that is being transmitted down the channel. This clock must be highly synchronized with the data or the receiving circuit will misinterpret the incoming signals. A phase lock loop (PLL) mechanism is often used to ensure that the channel’s timing clock and data flow are synchronized.
Jitter refers to distortion conditions that disrupt the synchronization between the clock and data. Jitter can be either random or deterministic. The PLL mechanism must be able to tolerate jitter to a certain extent so that it can recognize it, respond to it and remove it from the signal. Traditionally, jitter has been measured by an eye diagram on an oscilloscope. A strong signal with little jitter will have an eye diagram with narrow, distinct transitions from high to low voltage levels. As jitter increases in a channel, the transitions thicken and become fuzzy on the eye diagram because the jitter is distorting the clarity of the signal.
What Can ScanWorks Do?
Intel®’s IBIST (Interconnect Built-In Self Test) technology provides an effective example of how ScanWorks is able to access, automate and analyze embedded instrumentation. From within the ScanWorks environment, entire BERT tests can be executed through embedded IBIST instrumentation. Results are automatically displayed on the ScanWorks station.
ScanWorks' IBIST BERT GUI
Likewise, margining analysis can be performed on the ScanWorks platform using embedded IBIST instrumentation. Similarly to an eye diagram, a margining analysis is a plot with time and voltage axes that shows whether there is any margin in the communications channel or whether the channel has exceeded its voltage and timing margins.
The critical nature of signal integrity analysis during design validation and as a troubleshooting tool can not be overstated, especially as high-speed interconnects creep inexorably toward the 10-Gbps mark and as chip packages start looking more like a circuit-board-on-a-chip than the traditional single-die semiconductor. Capitalizing on its openness as well as its heritage of leadership in non-intrusive validation, test and debug, ScanWorks is fast becoming the outright leading platform in the new field of embedded instrumentation tools.
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