Hardware Validation

Data Mining Analytics for Serdes | HSIO Validation

Data Mining Analytics for Serdes | HSIO Validation

One-shot pass/fail validation testing won’t quantify the risk of faults on serdes and high-speed I/O (HSIO) buses, but data mining with statistical analytic tools will. In fact, you’ll see how close... more
System Marginality Validation DDR Memory and Serial I/O

System Marginality Validation DDR Memory and Serial I/O

Designing sufficient operating margins into today’s high-speed printed circuit boards has become a very tough job. Especially challenging are those high-speed serial I/O and DDR3|DDR4 memory buses.... more
Detection and Diagnosis of Printed Circuit Board Defects and Variances

Detection and Diagnosis of Printed Circuit Board Defects and Variances

Boards and chips keep getting denser, faster. And the speed is higher so they’re a whole lot more sensitive. Slight variances or defects cause intermittent crashes and performance degradation. And... more
High-Speed Non-Intrusive Board Test | PCIe, QPI

High-Speed Non-Intrusive Board Test | PCIe, QPI

Remember test pads? Small contact points on a board’s interconnect buses with physical access for test purposes? No more. Or at least not for high-speed serial interconnects like PCI Express, Fibre... more
Signal Integrity Validation for Intel® Core™ Platforms

Signal Integrity Validation for Intel® Core™ Platforms

Ever wonder why your notebook is running slower than ever, or keeps hanging and crashing? It could be signal integrity. Fortunately, Intel® Interconnect Built-In Self Test (IBIST) technology now... more
How to Avoid Poor Serdes Performance Caused By Circuit Board Manufacturing Variances

How to Avoid Poor Serdes Performance Caused By Circuit Board Manufacturing Variances

Validating prototype circuit boards gives you a level of confidence, but variances in manufacturing processes are just as likely to erode that confidence right along with the transfer speeds on high-... more
Intel® Microarchitecture Code Name Haswell Testability Review Using ScanWorks®

Intel® Microarchitecture Code Name Haswell Testability Review Using ScanWorks®

This document provides an overview of the use of boundary-scan test, processor-controlled test and high-speed I/O validation when applied to the Intel® microarchitecutre code name Haswell design.... more
How To Test High-Speed Memory With Non-Intrusive Embedded Instruments

How To Test High-Speed Memory With Non-Intrusive Embedded Instruments

One of the most pressing problems for system manufacturers is testing memory and memory buses on circuit boards. The speeds are simply too high, and signals get easily distorted when touched by... more
Signal Integrity Validation for Intel® Xeon® Platforms

Signal Integrity Validation for Intel® Xeon® Platforms

Performing signal integrity validation with traditional high-end capital equipment such as oscilloscopes is a very expensive proposition. Fortunately, Intel Interconnect Built-In Self Test (IBIST)... more
Bandwidth Tests Reveal Shrinking Eye Diagrams and Signal Integrity Problems

Bandwidth Tests Reveal Shrinking Eye Diagrams and Signal Integrity Problems

An old story compares the electronics industry’s unprecedented achievements with the automotive industry. If cars had kept pace with Silicon Valley, we could buy a vehicle with a V32 engine and... more
Platform Validation Using Intel® Interconnect Built-in Self Test | IBIST

Platform Validation Using Intel® Interconnect Built-in Self Test | IBIST

This paper describes the empirical results of platform validation using Intel® Interconnect Built-In Self Test (IBIST) and the ScanWorks HSIO product. Among the experiments conducted were: Bit Error... more