PRESS ROOM - AUTHORED ARTICLES

An Inside Job

by Glenn Woppman, ASSET InterTech, Inc. and Jeff Remmers, Business Development Consultant
Components in Electronics - CIE, (November 2008)

Advanced chip packaging is forcing instrumentation underground according to Glenn Woppman and Jeff Remmers.

It’s hard enough testing printed circuit boards (PCB) with chips that have little or no physical access for probes. Now that many advanced chip packages look more like PCBs-in-a-package than a single integrated circuit, the challenge to validate, characterize and test individual chips as well as the boards where they are placed has increased geometrically. A glimmer of hope on the horizon is an open industry standard, the IEEE P1687 Internal JTAG (IJTAG) standard, which, following its ratification, could provide the basis for open tools for testing these complex devices.

The increasing popularity of multiple cores, including internally developed and third-party intellectual property (IP) has made the process of testing SOCs more like testing an entire system in a single package than testing a single chip. Each individual core and every piece of IP must be accessed so it can be tested. To do this a variety of different test access mechanisms are being developed and adopted. Moreover, embedded microprocessors often implement custom, proprietary interfaces which call for a different test strategy from the rest of the SoC. However, in general, the IP that is integrated within a single-die (SoC) is of similar technology and, therefore, can be tested with similar methods.

New packaging technologies like System-in-Package (SiP) and Package-on-Package (PoP) are significantly more challenging than SOCs. These new packaging technologies feature multiple die of significantly different technologies, such as RF, digital logic, memory and others. In addition, the input/outputs (IO) from each die are often routed through the other die in the package, making the issue of visibility into the package’s or the system’s IO acutely difficult. In addition, devices placed in these new types of packages are exhibiting failure mechanisms that have not been seen in the more traditional single-die devices. Parametric characteristics including thermal stability, power leakage and others, as well as design-related structures are contributing to a higher device failure rate over the older, simpler types of devices. The failure rate of SiPs and PoPs is affected by a host of new, hard-to-test issues, often related to the interaction among the multiple die in a single package.

Inside Out

Increasingly, validating and testing complex packages is being done from the inside out, rather than from the outside in. Multiple die in a package means that the ability for a probe to make contact with the system’s or the chip’s device pins or IO is buried deep within the package.

As a result chip engineers have been adding DFT (design for test) structures to quickly test and provide advanced diagnostic capabilities for the chips at ATE test. These DFT structures include scan, memory built in self test (MBIST), logic built in self test (LBIST) as well as functional test structures using embedded processors as the access mechanism.

To overcome the limited visibility into these SiP and PoP packages, those DFT instruments that have been embedded into individual die are being employed at the package level to access, test and debug the internals of the chips. This embedded instrumentation is able to validate and test devices from the inside out, providing the results of their operation through an on-chip access port. Most often this access mechanism is the Test Access Port (TAP) which is defined in the IEEE 1149.1 Boundary-Scan Standard. The TAP is often referred to as the JTAG port after the Joint Test Action Committee and provides a standardized way for passing data between embedded instruments and an external test platform.

For the last three years, an IEEE working group in the U.S. has been developing a standard, IEEE P1687 or Internal JTAG (IJTAG), to act as a standard interface mechanism for all embedded instruments. This will allow for the development of open embedded instrumentation tools platforms that can interface to all IJTAG-complaint embedded instruments and then access, automate and analyses the output of the instruments. In addition, the use of the open P1687 standard will provide a platform for testing devices at various levels of assembly. The same tests deployed at wafer probe can be run at package test as well as during PCB assembly and even later at the system level. An open, industry-accepted standard enables test re-use throughout the system’s life-cycle.

Compounding the problem

For SiPs, PoPs and other multi-die packages, test methodologies are still evolving. Unlike PCBs, where devices are tested individually before they are mounted on a PCB and then the PCB is re-tested at this higher level of assembly, SiPs and PoPs are more difficult to test because of the limited ability to control or observe the IO pins of the individual die. One required technique that has been employed involves individually testing each die that is going into the package at the point of wafer probe. Then, the known-good-die (KGD) are assembled into a stack in a SiP. Unfortunately, it is increasingly becoming the case that individual die are often diagnosed as “No Trouble Found” (NTF), but once they are combined with other die in multi-die packages, the entire package exhibits failures.

Another issue this points up is the inability of today’s test methodologies to partition and analyses functionality, parametric performance and environmental effects in end systems. Parametric conditions like power fluctuations, thermal changes and the interactions of several die in a single-stack SiP can be tested at wafer probe while the die are being manufactured, but later following assemble into a multi-die package, these same issues cannot be tested.

For assembled SiPs or PoPs, test methodologies are still developing. Currently, these techniques are limited to system-level testing, which are usually inadequate for diagnosing failures at the individual die. The only option is to scrap the entire packaged system, writing off the cost of each individual die, the assembly process, the package and the time spent testing.

Another factor exacerbating the test process is the continually shrinking process geometries of chips. At the 65 nanometer (nm) process node and below, failure rates in chip production typically relate to the chip’s design structures, the libraries used and parametric performance. Moreover, failures in one area often contribute to failures in other areas, such as the optical and chemical processing of the device. In addition, the libraries used during design may have been optimized for a certain factor, such as power consumption, speed or die area, but these libraries will interact with adjacent cells, causing failures such as clock sag, voltage drops or other design-related failures. In assembled SiPs and PoPs, unforeseen anomalies in parametric characteristics can cause unexpected chip failures.

Fortunately, process nodes of 65 nm and smaller also mean that many more gates can be placed on a chip in the same amount of space. In many cases, chip designers are now taking advantage of these extra gates to embed the parametric and design instrumentation that will be needed to detect, diagnose and ultimately determine the root cause of failures in complex chips. As a result, monitors for power grids, ring-oscillators using Voltage Controlled Oscillators (VCOs) for process measurements and thermal characteristics, activity monitors for power consumption and other types of instruments are being embedded on-chip.

Technology and tools based on standards

The electronics industry has shown that basing a new technology on open standards, such as the IEEE P1687 IJTAG standard, is a sure-fire way for accelerating the adoption of that technology. Technology providers are encouraged to innovate to the standard and, just as importantly, standards encourage tools vendors to develop the tools that are so necessary to spur the adoption of a new technology. This is taking place with regards to embedded instrumentation and its use in testing complex, multi-die chip packages.

The solution that embedded instrumentation represents still has hurdles to cross. Silos of isolated embedded instrumentation are sprouting up in complex chips. For instance, instruments are being embedded for wafer probe, ATE package test, on-board bring-up and evaluation, in-system operation and others. The problem is that once an instrument has been deployed for a certain purpose, it may never be used again.

One solution would be a standard way of accessing and interfacing to embedded instrumentation. This would allow the same embedded instrumentation technology to be applied during every phase of a chip’s, a circuit board’s and a system’s lifecycle. This is precisely one of the goals of the IJTAG standard initiative.

Getting the Most Out of Embedded Instrumentation

IJTAG piggybacks on the existing JTAG standard insofar as access into the internals of a complex multi-die chip is provided by the JTAG TAP. At the same time though, the IJTAG working group has taken the position that the new standard should not force embedded instrumentation to conform to the IEEE 1149.1 JTAG standard. In addition, the developers of IJTAG do not want the deployment of the new standard to depend on changes to the boundary scan standard.

To achieve these two objectives, the IJTAG working group has defined a preliminary hardware architecture involving three distinct zones. Outward facing from the chip is the 1149.1 JTAG TAP. Facing inward to the internals of the chip, the JTAG TAP interfaces to IJTAG gateway mechanisms. These gateways provide access to the IJTAG-compliant embedded instruments. This middle gateway zone insulates the JTAG and IJTAG zones from each other, freeing each of these zones from the requirements of the other.

Currently the IJTAG preliminary standard has two major components. One is a hardware specification that defines two interfaces: first, the interface on the gateways between the IEEE 1149.1 boundary scan TAP and the embedded instruments; and second, the interfaces on the IJTAG instruments which allow them to be connected to each other. By standardizing this later interface, IJTAG instruments can be connected in a variety of configurations.

The second major component of the preliminary IJTAG standard is a language for controlling, managing and automating the operations of embedded instruments. This is referred control the embedded instruments, capture data from them and observe the results of their measurements.

New packages are here to stay because their benefits outweigh the challenges they present to test and validation engineers at both the chip and circuit board levels. Fortunately, the industry is coming up with new and innovative ways of coping with the increased complexities. Embedded instrumentation in general and the IJTAG standard (IEEE P1687) in specific hold much promise for overcoming many of these challenges.