Boundary
Scan Benefits Lead-free Assembly
By Alan Sguigna, ASSET InterTech, Inc.
SMT
Magazine, (March 2005)
OEMs and EMS providers are realizing the benefits of
using boundary scan in the face of initiatives such as
the move toward lead-free board assembly.
When the Joint Test Action Group defined the boundary scan
standard (IEEE 1149.1) more than a decade ago, the technology
was conceived of as a simple, low-cost way to test dense
circuit boards where physical access to device pins and test
pads was disappearing. Boundary scan since has evolved into
much more.
The four-wire, boundary scan interface has evolved into
a versatile infrastructure technology at the level of the
individual circuit board, and also is emerging as an integral
tool at the system level. It has become an invaluable embedded
communication technology, serving applications that were
not envisioned during its development. Boundary scan has
emerged as a foundational technology for an entire class
of test and programming methods, such as IEEE 1532 in-system
configuration (ISC) of programmable logic devices, in-system
programming (ISP) of flash memory, IEEE 1149.4 analog test,
emulation techniques, processor-based emulation testing and
IEEE 1149.6 testing of high-speed AC-coupled buses. OEMs
and EMS providers also are realizing the benefits of using
boundary scan in the face of initiatives such as the move
toward lead-free board assembly.
Riding Boundary Scan’s Coattails
One of the critical necessities for boundary scan to function as a board- and
system-level infrastructure for other test and programming techniques is
the functionality and ease-of-use of its support environment. With a powerful
boundary scan support system, the design, manufacturing or support group
is in a position to not only check for shorts and opens - originally the
most prominent purposes of boundary scan interconnect tests - but also to
perform a host of other test and in-system programming functions from the
same boundary tools environment. This increases efficiency, driving down
development and manufacturing costs.
The IEEE 1149.6 Standard for Advanced Digital Networks and
Intel IBIST (Interconnect Built-in Self Test) technology
are relatively new methods developed to test and validate
the design of high-speed serial buses such as Gigabit Ethernet,
PCI Express, Fibre Channel and others that have AC-coupled
LVDS signaling and speeds up to 10 gigabits per second (Gbps).
Both standards make use of a system’s boundary scan infrastructure.
Even the most hyperbolic supporter of boundary scan could
not have foreseen this eventuality more than a decade ago.
Figure 1. 1149.6 circuit
The IEEE 1149.6 standard specifies a method for applying
a system’s boundary scan capabilities to test a range of
high-speed interconnect buses with differential signaling
such as Gigabit Ethernet, Fibre Channel and others (Figure
1). As a result, a capable boundary scan environment can
perform both traditional test functions on DC-coupled buses,
as well as tests on high-speed AC-coupled buses, which are
becoming increasingly prevalent in certain types of computing
and communication systems.
Intel’s IBIST is a next-generation test method that is being
embedded into that company’s chips and chipsets. Its on-chip
test functionality depends on boundary scan (Figure 2) for
chip-to-chip communications, which is integral to its ability
to cost-effectively validate the design of high-speed bus
structures that include PCI Express and others.
Figure 2. IBST Test Flow
Another technology that has recently teamed up with boundary
scan to improve test coverage is processor-based emulation
test. For some time, emulators running on the processor to
perform functional tests on the system have used the boundary
scan interface on most microprocessors. Combining traditional
boundary scan testing with processor-based functional emulation
testing in the same boundary scan environment can extend
test coverage (Figure 3). In this arrangement, boundary scan
tests can be executed on complex logic devices, such as Ethernet
controllers that may not have boundary scan capabilities,
but can be accessed by the system’s microprocessor. These
two technologies, boundary scan and processor-based functional
emulation testing, form a synergistic relationship. In an
environment that combines two technologies, test coverage
is extended beyond what either one could provide solely.
Figure 3. eJTAG coverage
Many manufacturers also are turning to boundary scan as
a way to maintain high-test coverage while the industry transitions
to lead-free soldering compounds. Lead-free assembly complicates
circuit-board testing on several fronts. The in-circuit test
(ICT) systems that are deployed extensively in high-volume
manufacturing operations function by placing metal test probes,
or nails, onto test pads and/or device pins on circuit boards.
With a good electrical connection between nail probes and
the circuit board, the ICT system can exercise and test the
structural quality of the board.
Unfortunately, lead-free soldering techniques are more difficult
for ICT nail probes to penetrate, requiring increased force
on the circuit board’s test pads or device pins. This decreases
the useful life of an ICT fixture’s nail probes, driving
up test costs in high-volume manufacturing lines. Many electronics
manufacturers aim to reduce the amount of force exerted on
circuit boards during test to ensure product quality. It
makes sense that exerting less strain on circuit boards can
reduce the number of structural faults introduced by the
testing process itself.
Because JTAG tests do not require any physical access for
probes, or exert any strain on circuit boards, boundary scan
test techniques could help alleviate some of these difficulties.
Increasing boundary scan tests could decrease the number
of probes needed on ICT fixtures. Given the increasing expense
of durable nail probes for lead-free solder joint testing,
a reduction in the number used in an ICT fixture would cut
testing costs significantly. Moreover, simpler ICT test fixtures
could be produced faster, cutting a product’s time-to-market.
With fewer test probes, less strain would be placed on circuit
boards under test, reducing the possibility of introducing
faults during the test process.
System Tests with Boundary Scan
The benefits of boundary scan testing and in-system programming techniques
are not limited to the confines of individual circuit boards. In fact, more
manufacturers are realizing that individually testing each component part
of a system, such as circuit boards and other assemblies, does not ensure
a fully functional system once all of the boards and subassemblies are configured
as a system. For example, a connector could be faulty, or boards on a backplane
may be missing, out of place or simply not functioning properly in relation
to the backplane. Functional tests identify that the system is not functioning
as expected, but isolating and diagnosing the problem with functional tests
is time consuming, expensive and often based on trial-and-error. In contrast,
the diagnostic and fault-isolation capabilities of boundary scan are valuable
for testing, locating points of failure and troubleshooting the system as
a whole.
Boundary scan also can perform on-board programming of flash
memory, the in-system configuration of programmable logic
devices (PLDs) and on-board programming with I2C data. Beginning
with system-level debug and production test, boundary scan
provides many other system benefits when extended to field
support. For example, by reconfiguring on-board PLDs after
the system has been installed, boundary scan can be used
to update programs stored in flash memory or for updates
to system functionality.
Figure 4. System test
Boundary scan at the system level can be applied in a variety
of ways, but the most prevalent method is to design-in one
or more multi-drop boundary scan gateway devices that control
access to the multiple boundary scan paths located on individual
boards, backplanes and subassemblies in the system (Figure
4). These gateway devices can be controlled by an external
boundary scan test system that connects to the gateway device’s
boundary scan test access port (TAP).
Conclusion
Boundary scan has shown that it is a versatile and highly adaptable technology.
When implemented on circuit boards, backplanes and other subassemblies in
electronics systems, boundary scan can function as an embedded infrastructure
for a number of functions. Leading boundary scan vendors will continue to
improve tools and systems to take advantage of this embedded infrastructure.
Boundary scan vendors already have made great strides in terms of automating
the generation of test patterns and programming algorithms, while ensuring
the safety of the board or system from inadvertent electrical loads. The
ease-of-use of some boundary scan systems also has improved dramatically
with the inclusion of highly graphical user interfaces (GUIs) and step-by-step
assistance for new or occasional users.
If the past is any indication, boundary scan’s role in the
electronics industry will increase in the future as more
uses are found, especially as systems continue to offer powerful
enhancements, cost-effectiveness and ease-of-use.
Alan Sguigna, vice president of sales and
marketing, ASSET InterTech, Inc., may be contacted at (972)
437-2800; e-mail: asguigna@asset-intertech.com.
Surface Mount Technology (SMT) March, 2005
Author(s) : Alan Sguigna
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