Guidelines for Chip Design For Test (DFT) Based on Boundary Scan (JTAG)

In this document, we will look at DFT guidelines specific to the design of devices to be tested through the boundary-scan (JTAG) registers of IEEE 1149.1-compliant devices. Since the 1149.1 structures are incorporated inside the compliant devices, many of the guidelines relate to the specification of optional features inside the devices i.e. are device-level DFT guidelines. Accordingly, the first part of the document considers the device-level guidelines.

To view this PDF document, select here.