Bit Error Rate of Intel QuickPath Interconnect – Part 1

The required Bit Error Rate (BER) of Intel® QuickPath Interconnect (QPI) is 1 error in 10E14 bits. The BER threshold of PCI Express is 1 error in 10E12 bits. What might account for the two orders of magnitude difference?

Some of the underlying technology for Intel® QPI is found in the texts Weaving High Performance Multiprocessor Fabric and Mastering High Performance Multiprocessor Signaling, from Intel press, and both available on Amazon. The books are dated (published 2009 and 2010, respectively), but contain very interesting and useful nuggets on this fascinating bus.

The topology of QPI looks like this:

Further, it’s worthwhile to depict the QPI protocol stack, as well as physical layer “phits” and link layer “flits”:

Looking at the above diagrams, and understanding some of the basics of high-speed differential I/O, it is possible to construct a table which compares and contrasts some of the essential features of QPI and PCIe Gen3:

We’ll examine some of the underlying implications in an upcoming blog. In the meantime, there’s another interesting blog on QPI and some empirical studies of defects on differential high-speed I/O here.