In my last few blogs, I’ve talked about the challenges of
testing QPI, PCI Express, SATA 3, and DDR3 memory. These buses are common to
many Intel Sandy Bridge and Ivy Bridge motherboard designs. Should test engineers
take chances and just not test them?
Let’s look at memory test challenges, as an example, as
highlighted in my blogs How to test DDR3 and DDR4 memory: Part
1 and Part
2. As memories and other buses speed up, and designs become more complex
and dense, the effect of any kind of structural or at-speed defect becomes more
pronounced. Serial I/O may in general be self-healing, but shorts and opens will
degrade the link speed and/or width; and other defects, like induced crosstalk,
will invisibly affect overall bus performance. And parallel buses, like DDR3,
handle such defects by incurring performance overhead to detect the errors, and
possibly crashing the system (to avoid, for example, your bank account
erroneously being credited with deposits you didn’t make!).
Detecting the broad spectrum of defects, ranging from
structural, to functional, to performance-impacting faults, is impossible for
any one test technology. In fact, the only sure-fire way to de-risk a product
launch is with a combination of boundary scan (structural),
processor-controlled test (functional), and Intel HSIO (performance)
technologies. To see how these were put in action for the previous Intel micro-architectures,
check out the whitepapers on Xeon
5500 and Xeon
7500. And an entertaining video on this subject can also be seen here: http://www.asset-intertech.com/News/For-Working-Media/Videos/Testing-Intel-Xeon-5500-Core-i7-(Nehalem)-platform. And with Haswell just around the corner, this is becoming most important.
