Isn’t it a great time to be a board designer? Compared to twelve years ago, the average number of nets has gone from 1,544 to 2,832; the number of pin-to-pin connections has increased from 7,661 to 13,573; the number of components has grown from 1,120 to 3,518; and many other challenges to the job have arisen.
Mentor Graphics does a survey for their annual PCB Technology Leadership Awards where they assess trends in board design. You can read more about the Mentor TLA here: http://www.mentor.com/products/pcb-system-design/tla/. This program has been running since 1988, and as part of the awards they survey numerous board design teams and pull out useful statistics. A summary of these are in this table:
|
Design Trend |
1999 |
2011 |
|
Total metal layers |
10 |
14 |
|
Total area (in2) |
76 |
81 |
|
# nets |
1,544 |
2,832 |
|
# pin-to-pin connections |
7,661 |
13,573 |
|
# components |
1,120 |
3,518 |
|
# component pins |
5,790 |
13,314 |
|
Average leads/in2 |
89 |
387 |
It seems to me that design and verification tools in the board design space haven’t kept pace with this astonishing growth in density and complexity. Semiconductor designers seem to enjoy regular enhancements to their design, synthesis and simulation tools, but in the board design world we’re stuck with essentially the same tools that have been around for a long time.
The good news is that test and measurement tools have taken up the slack. The newest board tools, of course, are based upon the wonderful array of new test instruments that are embedded within semiconductors on the board. These PCB tools avoid the restrictions of legacy nails- and probe-based access by taking advantage of the Built-In Self Test (BIST) engines inside the chips, courtesy of the semiconductor EDA industry and chip designers. Validation, test and debug tools such as JTAG/boundary scan, on-chip debug, memory BIST, and SerDes BIST all ride the Moore’s Law curve associated with chips.
