I read an interesting paper recently suggesting that IEEE 1687-based tests were best run at ICT on the manufacturing floor. The article was, of course, written by an ICT vendor. This is patently not true and is even a little bit preposterous. Let me explain…
First, a little bit of background. IEEE P1687 is a preliminary standard for access and control of instrumentation embedded within semiconductor devices. For many years, chip makers have routinely embedded test and measurement functionality into their devices for their own needs to characterize, validate and test their chip designs. The IEEE P1687 standard seeks to leverage this embedded instrumentation for lifecycle validation, test and debug of chips, circuit boards and systems. Because the standard makes use of the IEEE 1149.1 boundary-scan (aka JTAG) standard for physical access to embedded instruments, the new IEEE P1687 standard is most often simply referred to as the Internal JTAG or IJTAG standard. ASSET’s chief technologist, Al Crouch, is the co-chairman of the IJTAG standard working group.
So what does this have to do with ICT? Good question. In the article http://www.circuitsassembly.com/cms/magazine/207-2010-articles/9447-the-proposed-ieee-test-standards, it is suggested that on the production floor IJTAG will most commonly be deployed on ICT. This suggestion ignores any power, loading, or cooling considerations that are the bane of ICT-based testing.
For circuit board test, IJTAG will be used to drive Memory Built-In Self Test (MBIST), Logic BIST, and I/O BIST engines within chips. Running these BISTs requires that the chips are populated, powered up, and running at full-speed.
This is where it gets nasty for ICT. Many ICT tests are run without processors installed, which of course eliminates the possibility of using IJTAG. Where they are installed, they need cooling and power (the latter of which may exceed the capacity of some older-style ICT). But really, in almost all cases, device cores do not run at ICT, which means that they dissipate only a small fraction of their normal operating power.
Try to run these BISTs on ICT and you’d have to deal with a plethora of problems. While it is possible for clocks to be developed either on the PCB or in the fixture, signal integrity and noise issues at ICT frequently make this not a good idea. Bed of nails fixturing was a good idea when things operated at frequencies approaching DC. But nowadays, many defects, particularly on high-speed I/O like PCIe Gen3, DDR3, SATA III, etc. will only manifest themselves at-speed anyway. And although there’s in general no reason that boards can’t have heat sinks on them at ICT, this gets tricky – access issues pop up, and with vacuum fixtures there is little air around the board to move the heat from the heat sinks.
The solution, of course, is to run IEEE P1687 tests downstream of the ICT, at functional test. Then the power of IJTAG can be used to perform structural, functional, and performance routines to maximize overall system test coverage. ICT or MDA (manufacturing defect analysis) can still be used upstream to provide low-level structural test coverage, where access permits.
