Richardson, TX – ASSET® InterTech, Inc., the leading supplier of open tools for embedded Instrumentation, will integrate test adapter intellectual property (IP) from IPextreme into its ScanWorks® platform for embedded instruments to enable chip and circuit board tests under the new IEEE 1149.7 reduced-pin boundary scan standard.
“IPextreme leads the market with the industry’s first IEEE 1149.7 synthesizable IP,” said Pierre Xavier-Thomas, vice president of engineering, IPextreme. “We are excited about working with ASSET to accelerate the availability of IEEE 1149.7 tools in the marketplace. This will enlarge the IEEE 1149.7 ecosystem and benefit end users.”
The IEEE 1149.7 standard requires fewer pins on the chips where it is implemented than does the original IEEE 1149.1 boundary scan standard. IEEE 1149.1 is often referred to as JTAG after the Joint Test Action Group which initiated the original specification. The IEEE 1149.7 standard, which was approved in December 2009, enhances the original IEEE 1149.1 boundary scan (JTAG) standard with new test and debug capabilities particularly well suited for testing system-on-a-chip (SoC) devices, multi-chip modules and stacked multi-die chips. Backwards compatible with IEEE 1149.1, IEEE 1149.7 can implement a standard JTAG interface with two pins in lieu of four.
“We expect IEEE 1149.7 to have a significant impact in the mobile market where printed circuit board real estate is at a premium and test access scarce,” said Adam Ley, ASSET’s chief technologist for boundary scan and a major technical contributor to the IEEE 1149.7 standard. “IEEE 1149.7 is also invaluable as an enabling technology for tests that take advantage of embedded instruments in complex silicon. With IPextreme’s contribution, ScanWorks will be able to access and control these instruments via IEEE 1149.7.”
“Texas Instruments, a major contributor to the IEEE 1149.7 specification, worked closely with companies such as ASSET to accelerate the adoption of this technology in the test industry,” said Gary Swoboda, chief technical officer (CTO) of emulation technology at TI. “There is a growing ecosystem of semiconductor IP, verification suites, and chip and board test tools for IEEE 1149.7.”
ScanWorks® – Platform for Embedded Instruments
ASSET, through its ScanWorks platform, is applying the experience it has gained from two decades as a leading supplier of IEEE 1149.1 boundary-scan (JTAG) test tools to the development of open embedded instrumentation tools. The boundary-scan infrastructure that is embedded into chips and circuit boards is one of several technologies which can form the basis for an embedded instrumentation toolset. In recent years, ASSET has significantly enhanced ScanWorks beyond boundary-scan test with the addition of other embedded instrumentation technologies, including processor-controlled test (PCT) and tools for Intel® IBIST (Interconnect Built-In Self Test), an embedded instrumentation technology that Intel® and other companies are embedding into next-generation chips and chipsets.
About ASSET InterTech
ASSET InterTech is the leading supplier of open tools for embedded instrumentation for design validation, test and debug. The ScanWorks platform provides automation, access and analysis tools in one environment. Users can quickly and easily validate and test semiconductors, circuit boards or entire systems during every phase of a product’s life, including design, manufacturing/repair and field maintenance. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.
For product information, call 888-694-6250, fax 972-437-2826, e-mail ai-info@asset-intertech.com or visit www.asset-intertech.com.
Trademarks ASSET, the ASSET logo and ScanWorks are registered trademarks of ASSET InterTech, Inc. Intel, Intel Xeon, Intel Itanium and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. All other trade and service marks are the properties of their respective owners.
