SPI Flash/EEPROM Programming Using FPGA and JTAG

A ScanWorks Platform Application Brief

Onboard SPI Flash memory can be programmed effectively via either of two methods:

1. Through the boundary-scan chain of a connected FPGA
2. Using a SPI master IP (Intellectual Property) as an embedded instrument inserted into the FPGA

The first method of programming through the FPGA’s boundary-scan chain is relatively slow, yet simple and flexible for small memories. However, a SPI master IPprograms at very high speeds for any amount of data, any size FPGA and any size memory device. And that translates into dramatic cost savings in manufacturing.

This application brief describes and compares these two methods, using as an example the programming of 1MB of data into a Micron SPI Flash device (M25P80) from a Xilinx Spartan 6 FPGA (XC6SLX16-2CSG324C).

Highlights:

• Boundary-Scan Chain Access Method
• SPI Master IP with FIFO Memory
• Programming Time Comparison
• Manufacturing Cost Savings
• Summary & Conclusions