Manufacturing Test Archives | Page 3 of 6

New eBook shows how to avoid conflict among embedded test access ports when integrating SoC IP blocks

Wednesday, April 8, 2015

Cores and other blocks of intellectual property (IP) often feature a test access port (TAP). When multiple such IP blocks are integrated into a system-on-a-chip (SoC), their TAPs become embedded. Such embedded TAPs (eTAP) are prone to conflict with each other, which can prevent engineers from accessing IP blocks…

How to do at-speed functional verification of serial interfaces without functional software is described in new eBook

Tuesday, March 11, 2014

Richardson, TX – Historically, verifying the at-speed functionality of serial interfaces on prototype circuit boards has required the system’s functional software. But the functional software is often not ready yet when prototypes arrive. That means delaying the product’s migration into manufacturing. A new eBook published by ASSET® InterTech describes…

Programming on-board flash and EEPROM memory at SPI bus speeds from an FPGA is explained in new eBook

Wednesday, September 4, 2013

Designers and manufacturing engineers face challenges when it comes to programming flash and EEPROM memories that are already soldered to a circuit board. Often, the software or firmware content of these memories has not yet been completed when hardware prototypes are being validated and tested prior to volume manufacturing.…

Testing DDR3 memory with boundary scan / JTAG explored in new eBook by ASSET InterTech

Tuesday, August 6, 2013

ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, has issued a new eBook on how to test DDR memory with non-intrusive JTAG or boundary-scan (IEEE 1149.1) methods. A recent survey of engineers by the International Electronics Manufacturing Initiative (iNEMI) found that testing memory soldered to circuit…

ASSET’s new eBook explains how to recover the costs sunk into circuit boards that will not boot

Thursday, June 6, 2013

A new eBook from ASSET® InterTech will help circuit board manufacturers who want to recover their investment in assembled boards that won’t boot – so called dead boards – and still maintain the tight production deadlines that constantly reduce the time they can spend on board debug. Even though “How…

ASSET ScanWorks is among the first tools to support the new on-chip Intel Silicon View Technology

Monday, June 3, 2013

With the introduction today of Intel® Silicon View Technology (Intel® SVT), ASSET® InterTech’s ScanWorks® platform for embedded instruments becomes the only platform in the industry that fully supports all three aspects of the new validation, debug and test capabilities which Intel is embedding into its processors and chipsets. Based…

How to do functional tests on I2C and SPI monitors with JTAG is explored in new eBook from ASSET InterTech

Wednesday, May 8, 2013

A new eBook from ASSET explains how the structural test methodology based on the IEEE 1149.1 boundary scan standard, known as JTAG, can apply functional tests to I2C and SPI system monitors during prototype board bring-up and later during circuit board production. Devices such as temperature sensors, electrical sensors and…

New PXI controller for ASSET’s ScanWorks platform supports four test technologies

Tuesday, April 23, 2013

With the new PXI-based controller for ASSET® InterTech’s ScanWorks® platform for debug, validation and test, engineers can test circuit boards with four different toolsets, each based on a different test technology. Operating from a personal computer and a PXI chassis, the new ScanWorks PXI-1000 controller can apply boundary-scan tests…

New eBook explores CPU cache-as-RAM for board bring-up of non-booting prototype circuit boards

Tuesday, February 26, 2013

A new eBook from ASSET® InterTech, the leading supplier of tools for embedded instrumentation, takes a close look at how run-control tools can employ a processor’s on-chip cache memory instead of on-board RAM memory to boot non-booting prototype circuit boards. “Designers often face a catch-22. They have to diagnose a…

ASSET white paper explores solutions for diminishing test coverage from in-circuit test (ICT) systems

Wednesday, December 19, 2012

Non-intrusive software-based test methods deliver test coverage beyond the reach of legacy probes and bed-of-nails testers. A new white paper from ASSET® InterTech explains why test coverage from intrusive, probe-based in-circuit testers with their bed-of-nails fixtures is diminishing. The paper also describes software-based non-intrusive methodologies that test from the…

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