Statistical analytics goes beyond pass/fail testing to quantify the risks in a new design
A new eBook published by ASSET® InterTech demonstrates how the data mining of validation test results can reduce the time an organization spends on validating serdes high-speed I/O (HSIO) buses and, at the same time, predict the risk of failure inherent in new designs.
“Chip vendors like Intel® and others have shown that the best practice for validating HSIO buses calls for statistical analytics on a database of test data from applying the same test several times on multiple prototypes. This ‘NxN’ methodology far surpasses the traditional one-time pass/fail testing when it comes to quantifying how close a certain bus or lane on a bus is to failing in the hands of users,” said Tim Caffee, ASSET’s vice president of design validation and test. “Data mining also allows the organization to reduce the time it spends on validation testing by standardizing the process across multiple teams, improving test stress quality, and establishing a baseline across the product life cycle.”
The new eBook, titled “Data Mining Analytics for Serdes HSIO Validation – Moving Beyond Pass/Fail” explains that passing a one-time pass/fail validation test does not give the designer an indication of the risk of failure throughout the system’s life cycle. The eBook is free and available for downloading now from the eResources section of the ASSET InterTech website, “Data Mining Analytics for Serdes HSIO Validation – Moving Beyond Pass/Fail“.
Other informative eBooks, white papers and videos on issues relating to chip, board and system debug, validation and test also can be downloaded from our eResources.
