Learn what IEEE 1149.7 is all about, what its objectives are, how it works, its implications for debugging SoCs and 3D chips, and for testing circuit boards. Several illustrations show IEEE 1149.7 topologies. Scan-state sequences and flow charts clarify IEEE 1149.7’s terminology.
The IEEE 1149.7 standard reduces the pins and enhances the functionality of the IEEE 1149.1 standard’s Test Access Port (TAP) and boundary-scan architecture. It offers a mechanism that is well suited for accessing multiple cores on SOCs, multiple die in 3D chips and SIPs, and multiple packages in POPs.
Find out directly from the experts about valuable IEEE 1149.7 features like hot-plug immunity, power management, optimization of scan throughput, and access to debug instrumentation.
IEEE 1149.7 JTAG Tutorial: