Testing DDR3 Memory with Boundary Scan/JTAG | eBook

A recent survey asked test engineers to identify their biggest circuit board test problems. Among the top three answers were characterizing and testing soldered-down memories!

Clearly, the ability to thoroughly test, characterize and diagnose faults and failures with soldered-down memory is one of the most pressing problems in the industry. Using DDR3 memory as an example, this eBook discusses how boundary scan test and JTAG methods based on the IEEE 1149.1 standard can be an effective solution.

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