Page Translation Window Introduction

The Page Translation window is used to look at the memory paging feature of a processor. The window displays a pictorial representation of the address translation process that occurs in paging. The exact representation in the window may change as different varieties of paging are in use (e.g., 4K vs. 2M pages) or the processor type (e.g., Intel or AMD), but, in general, it is a good representation of what is displayed. To open the Page Translation window, go to View|Page Translation or click on the Page Translation icon on the toolbar.

Page Translation dialog box (AMD processor)

 Page Translation Window Elements

Address Field

The Enter address to translate field allows entry of address in various formats (e.g., linear, segment:offset, selector:offset, segment register:offset). This address is translated into a linear address and inserted into the Linear field.

Linear Fields

The Linear fields are displays of the resultant linear address from the Address field. The display is in binary, divided into the various components.  The hex value is shown to the right.

The Linear address is divided into various components that depend on page size or processor type. As a result, Page Map Level 4, Page Directory Pointer, and Page Table may not be visible.

Tables

The Page Translation dialog box allows scrolling in the Page Map Level 4, Page Directory Pointer, Page Directory and Page Table fields. This enables exploration of the mapping of pages without having to enter a new value in the Address  field. Simply click the mouse on or scroll to an entry in the one of the table list boxes, and the corresponding entry is activated.

The entries in these tables are color-coded, which speeds up the interpretation of the table state and structure.

• Grey = Not Present

• Black = Present

• Blue - Accessed

• Red = Dirty

Placing the cursor on a current value causes a flyover tooltip to display the attributes of the entry.

Page Frame

This field displays the resultant translated physical address of the corresponding linear address. In some cases the linear and physical addresses may be the same.