What’s the difference between circuit board structural test and functional test? And how does test coverage relate to diagnostics? These terms are sometimes used interchangeably, but not knowing the difference may result in a less-than-optimal test methodology. Let me explain…
“Structural test” is often defined as verification of an assembly process by testing each of its smaller elements and their interconnects. Structural test tools include Advanced Optical Inspection (AOI), Advanced X-Ray Inspection (AXI), Digital Multimeters (DMM), Manufacturing Defect Analyzers (MDA), In-Circuit Testers (ICT), boundary scan (JTAG), Flying Probe Testers (FPT), and others. AOI and AXI are inspection tools as opposed to test tools as they use visual technologies. DMM, MDA, ICT, JTAG and FPT use electrical test technologies to perform their functions. Although these technologies are often evaluated in terms of their “shorts and opens” detection capabilities, it’s important to consider that they must also verify the “rightness” of the components on a printed circuit assembly.
When discussing “structural test coverage”, we look for a way to deterministically express the fault detection capabilities of a test methodology on a given board design. The categorization of structural defects for devices and interconnects can be, for example, articulated using iNEMI’s PCOLA/SOQ approach:
Component Scoring Guidelines
| P | Presence | Does the test determine the presence of the part? |
| C | Correctness | Does the test determine that it’s the correct part? |
| O | Orientation | Is the part oriented properly or is the polarity proper? |
| L | Live | Is the part electrically functional for basic activity? |
| A | Alignment | Can the test determine lateral displacement or minor rotation? |
Interconnect Scoring Guidelines
| S | Shorts | On an interconnect, can shorts within a shorting radius be detected? |
| O | Opens | If there is an open on the pin/trace will there be a test failure? |
| Q | Quality | Is the quality of the solder, wetting, and general structural integrity of the circuit board sufficient? |
So, the test coverage of a given structural test methodology (which itself consists of one or more structural test tools) can in principle be determined by looking at all of a board’s parts and pins and filling in the blanks for PCOLA/SOQ. The higher the number, the higher the test coverage. Appropriate weighting can be added for “critical” devices or interconnects.
Structural test, in and of itself, does not constitute a complete test methodology. It is entirely possible that the board is structurally sound, but it does not function! This is of course where functional test comes in. Functional test provides verification that a design will perform its designated function. It is far more subjective than structural test in that it is extremely difficult to verify the complete functionality of a complex electronics system in all conceivable operating conditions. Functional test methodologies vary substantially from product to product and company to company. For example, on a low-end cell phone, functional test may consist simply of turning the phone on and verifying its ability to receive a call. There may be no structural test applied to a system like this at all! On the other hand, a high-end wireless basestation may be subjected to a comprehensive battery of functional tests. These tests may verify not only that the system is working properly, but may also stress it to evaluate its performance under load and its conformance to whatever industry specifications govern its operation. Such performance and conformance tests are primarily applied in a system’s design validation at prototype stage, but some OEMs will apply these test technologies in the manufacturing process as well to ensure the utmost in quality.
In order to capture test coverage metrics from functional tests, iNEMI in 2009 introduced the FAM defect categorization:
Functional Scoring Guidelines
| F | Feature | Can presence or absence of a feature be detected? |
| A | At-speed | Can the pin/interface/feature be tested at min/mid/max speeds? |
| M | Measurement | Can a measurement be taken that confirms performance to a BER, CRC or other requirement? |
So put together, PCOLA/SOQ/FAM represents a comprehensive expression of the amount of coverage obtained through a combination of structural and functional test technologies.
Put another way, PCOLA/SOQ/FAM scoring articulates a test engineer’s defect capture probability. Deterministically, any defect which escapes the factory will be due to a test strategy which is incapable of detecting that fault on the affected part(s) and pin(s). Since it is impossible to create a test strategy which will capture every conceivable fault for every possible permutation of temperature, voltage, process, and operating conditions, it’s the test engineer’s responsibility (and some would say, art) to achieve the maximum test coverage at the lowest possible cost.
The astute reader will have noted at this point that functional test technologies can in fact contribute to the structural PCOLA/SOQ score for a given board design. Hook up, for example, an IP traffic generator/analyzer to a router and you’ll probably find out fairly quickly if there’s a short circuit anywhere on one of the data lines of the routing silicon, control plane processor, PHYs, or other parts. Symptoms will of course vary depending on the nature of the defect and the test: maybe there’s packet loss, or packet latency is high, or there’s lots of jitter. So functional test technologies have the advantage of contributing to both the FAM and the PCOLA/SOQ metrics for test coverage.
But the limitations of conventional functional test lie in diagnostics. As described above, a structural defect may manifest itself in a gross failure in system operation. There is no way that the traffic generator/analyzer can correlate packet loss to for example an open circuit on device U24 pin 87. Its test coverage may be high (which is good – a fault can be discovered by the OEM and not by their customer) but its diagnostic granularity is low (which is bad – the OEM cannot determine the root cause of the failure and take corrective action, which means the board goes into the “bone pile”).
In an era of diminishing test coverage from structural test technologies such as ICT, and faced with inadequate diagnostics from traditional functional test, what is a test engineer to do? The answer lies in embedded instrumentation within silicon. A functional test technology such as processor-controlled test leverages off of a board’s CPU to perform register tests and fully exercise its devices and buses. The low level of such tests can in most cases indict faults to the defective parts, nets and even pins. And on Intel® board designs, Intel’s embedded IBIST IP can provide extremely high levels of both FAM and PCOLA/SOQ test coverage (covering a fault spectrum which is impossible to achieve with other technologies) whilst isolating faults to the part and lane level.
Ultimately, embedded instrumentation-based technologies will replace the test access lost by legacy structural-only testers, and at a much lower cost. And, because on-chip instruments can exercise their connections functionally, they provide the bonus of FAM coverage in additional to PCOLA/SOQ. With high test coverage, excellent diagnostics and lower cost, the trend is clear.
