Validating high-speed serdes transmission lines on prototype
circuit boards will certainly give you a level of confidence in the design. The
problem is that this confidence can quickly erode during volume manufacturing
because of the variances inherent in manufacturing processes. If undetected,
these variances can increase warranty returns and repair costs downstream.
We’ve just written a new e-book that explores this problem and describes
solutions.
I collaborated with Arden Bjerkeli, ASSET’s director of
customer experience, on an e-book entitled “How
to avoid poor serdes performance caused by circuit board manufacturing
variances”. The problem can become acute because undetected variances lead
to a host of defects, such as pin holes, breakouts, under-etching,
over-etching, opens, shorts, spurious copper, spurs, traces too close together,
incompletely plated vias, annular ring breakout, variances in plating
thickness, delamination and many more.
Unfortunately, the validation techniques that design
engineers use on prototypes usually involve oscilloscopes or vector network analyzers.
And these types of external testers don’t deploy well in high-volume
manufacturing settings where test time is critical. Embedded instrumentation
offers an effective alternative because margining and bit error rate tests can
be performed on samples of production boards without slowing the manufacturing
line significantly.
Check out this informative e-book, "How to avoid poor serdes performance caused by circuit board manufacturing variances".
