Trace resources within chips allow for viewing of executing code and processor events. Intel processors support facilities such as Last Branch Record (LBR), Branch Trace Store (BTS), and Architecture Event Trace (AET). What are these?
Hardware-assisted debug tools with trace capability augment basic source-level debug functionality such as halting the processor, single-stepping through code, and peeking/poking at register and memory values. Trace allows for looking backwards in time at code and events to help determine the root cause of system misbehavior. On some Intel processors, three main trace resources are available: LBR, BTS and AET.
LBR stores a very limited amount of trace information (typically 4 – 16 branch locations) inside model-specific registers (MSRs). It has virtually no overhead.
BTS uses cache-as-RAM (CAR) or system DRAM to store many more instructions and events, limited only by the amount of memory on the target system. Unlike LBR, BTS overhead impact is anywhere from 20% to 100%.
AET offers more selective tracing than LBR or BTS, and the trace data can be funneled through the processor’s XDP port. Examples of selectively traceable architectural events are interrupts, exceptions, read from model-specific registers (RDMSR), write to model-specific registers (WRMSR), IN/OUT instructions, code/data breakpoints, system management interrupt (SMI), and MWAIT. Overhead depends on the scope of the trace data, but can be huge if all events are captured.
Used together, LBR, BTS and AET provide a comprehensive set of on-chip embedded instrumentation for engineers who want to find bugs fast and develop high-quality code.
A more in-depth treatment of this topic is available here: http://www.asset-intertech.com/Products/Software-Debug-and-Trace/Faster_Firmware_Debug_Intel_Embedded_Trace_Tools.
