At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?
PCI-SIG’s marketing workgroup chair, Ramin Neshati, interviewed with The Register about the status of PCI Express 4.0 a couple of weeks ago at their developers conference. This new specification will double lane bandwidth to 16GT/s, while preserving the same 128b/130b encoding scheme of PCIe 3.0, continuing to work with standard FR-4 glass epoxy PCBs, and remaining backwards compatible all the way back to PCIe 1.0.
Physics, however, does apply some limitations. PCIe Gen3 can be made to run up to 16-20 inches if design care were taken. PCIe 4.0, on the other hand, is expected to have a maximum trace length of 10-12 inches. It’s simply impossible to use low-cost FR-4, pass through two connectors, and retain enough signal integrity at these speeds; no matter how robust the transmit and receive equalization schemes at the source and endpoint devices are.
There is a solution, though: as with PCIe 3.x, PCIe 4.0’s range can be extended with extension devices, otherwise known as retimers. PCI-SIG is actively working on ECNs to update the requirements for these devices at PCIe 4.0 speeds. Essentially, a retimer acts as a repeater, operating at the physical layer to fine tune the signal using Continuous Time Linear Equalization (CTLE), Decision Feedback Equalization (DFE), and transmit final impulse response equalization (Tx FIR EQ, or just TxEQ). Retimers are completely transparent to the data link and transaction layers.
So, to achieve a 20-inch range, one simply places retimers per every ten inches.
Of course, margining the links to/from the retimers is critical, to ensure that the links are healthy and there is sufficient margin in the system. This is because no equalization scheme is perfect. It is known that crosstalk is exacerbated by transmit pre-emphasis and de-emphasis. And, at the receiver, CTLE also amplifies crosstalk noise.
It is also expected that PCI Express devices operating at these speeds will exhibit more variance in performance, so testing with a range of source and endpoint chips will be important. To read about the sources of this variance, read our white paper here: System Marginality Validation of DDR Memory and Serial IO.
Finally, any sort of structural defect, such as a short or open, is unlikely to be compensated for fully by retimers. To review the effects on shorts and opens on system margins, check out our eBook here: Tutorial on Board Test of DDR3/DDR4 Memory and Serial I/O.
