As high-speed differential buses on today’s board designs become faster, the maximum allowable PCB insertion loss declines. What causes this effect, and how can it be mitigated?
The insertion loss of a PCB is generally defined as the total loss of its transmission lines. It is well-known that insertion loss increases with signal frequency, as per the below example*:
* Graph courtesy of the EDN article, What PCB material do I need to use for RF?
The above graph contrasts the measured loss per inch of standard "glass epoxy" FR-4 PCB material, versus a low-loss, high-frequency Rogers RO4350B material. It can be seen that at higher frequencies, such as for PCI Express Gen3, Intel QuickPath Interconnect, and other differential buses, the frequency response difference is significant.
Higher PCB insertion loss can, depending on the design, lead to a collapse of the channel margin. More attenuation will close the eye vertically. And as transitions become less sharp, there will be more horizontal closure of the eye, and the timing interval may collapse.
To address this, it is necessary to specify the maximum allowable insertion loss to the PCB supplier. PCB loss can be reduced by:
- Using wider traces
- Providing for looser coupling (that is, greater spacing between traces)
- Delivering thicker dielectrics (more laminate/prepreg layers and thicker layers)
- Lowering the PCB material dielectric constant
The first two items tend to decrease routing density, which in turn usually requires more board layers, which can drive PCB cost up. And the third item also increases cost.
And the last item implies moving to more exotic materials, which also drives cost up.
There are numerous other factors that will affect insertion loss, including temperature, humidity, trace surface roughness (a major contributor), board topologies (i.e. routing lengths, number and type of connectors, via effects, backdrilling), any defects and variances within the board, etc. All of these need to be taken into consideration to ensure that system margins are acceptable. Further, the silicon itself eats into operating margins, and must be taken into consideration when providing insertion loss guidelines to the PCB supplier. In fact, it is known that the devices themselves contribute the majority of margin variance on any given design. An empirical study describing this last effect can be read in our white paper, Margins (Eye Diagrams) Follow the Silicon.
Mitigating these effects can be a challenge. It is always desired to keep costs down by continuing to use good old FR-4 and minimizing the number and thickness of layers. I'll write further on some design practices to help with this in a future blog.
