Using new silicon is always challenging, especially when the silicon is an SoC and has so many intriguing features, and Design Engineering is trying to use them all. The Zynq UltraScale+ MPSoC from Xilinx is no exception, and the 1,100 plus pages of the Technical Reference Manual (TRM) is a testament to its sophistication/complexity and features. At ASSET, we are determined to help Design Engineering and Production Test engineers with managing the complexity caused by choosing a SoC, and providing a test tool environment that supports prototype and production circuit board tests. To accomplish this, the tool needs to be designed by engineers with a passion for keeping the tool interface intuitive and increasing engineering productivity.
ASSET’s new tool (called PFx) for the Zynq UltraScale+ has just been announced. Naturally, there are marketing data sheets that discuss the product. But to get below the thirty-thousand-foot view of the tool, we have decided that we would publish, in addition to the data sheet, the Quick Start Guide for PFx on the UltraZed ZUxEG board. Here are some highlights:
- DDR memories test with nine different memory tests to choose from
- Programming SPI and SD/MMC memories at near device programming speeds
- At-speed functional test coupled with boundary scan test
All these elements are shown in the eBook and the guide is a step-for-step document on how to use ScanWorks on the UltraZed ZUxEG board. This guide, coupled with your UltraZed knowledge, will provide more insight when dealing with design and production challenges with your Zynq UltrasScale+ MPSoC designs.
