Recently as ASSET is a 3rd party tool supporter of Xilinx FPGAs for a number of applications, I was reviewing the Xilinx community seeing a lot of users trying to use Vivado and Platform Cable USB II pod for production in-system programming with less-than-optimal results or no results at all. First, Xilinx says the Platform Cable USB II with Vivado/SDK as the UI, is to be used for prototype programming and is a design tool, not a production tool. Some of the issues you run into trying to use Vivado/SDK and the Platform cable USB II are:
- Difficulty targeting flash devices in bare metal applications and Uboot is not an option
- Customer comment – My application is bare meatal and Uboot serves no purpose
- Not wanting to use the SDK in Production
- Customer comment – SDK isn’t even terribly viable in production because one has to have a project before one can flash a PROM.
- Needing Windows (not Linux) support in production
- Programming failures due to DDR target issues
- Controlling the image download rate in production
- Difficulty in getting the hardware design and the software driver to work
I recently undertook a project where I tried to program some flash devices on a Zedboard using the Xilinx tools (Vivado and SDK) and after weeks of work, the results were much less than my expectations.
The devices that I tried to program were the QSPI which is connected to the Zynq-7020PS, a QSPI device connected to the PMOD header JA1 (which is connected to the Zynq-7020PL), and the SD card.
Using the Workshop for Beginners from Avent I worked thru the exercises until I had an application that I could program into the QSPI (IC15). That’s when I realized that I couldn’t just program the device with the tool chain without creating a First Stage Boot Loader (FSBL) and including the application in the FSBL package. I also discovered that the code for programming the QSPI is embedded in the PS7_init software created in Vivado when the design is created. So, the code downloaded by the SDK tool is loaded into DDR and then executed to program the QSPI with the FSBL and application. The methodology assumes that not only is the SoC properly fitted but, so is the DDR memory devices and the QSPI device correctly fitted. That is a big assumption in production. This was just the beginning of my discoveries and frustrations.
Here’s a Better Way
As I highlighted there are many problems trying to use Vivado in-production for device programming, SO DON’T DO IT AS XILINX HAS STATED! I did some in-depth research using Vivado and Platform Cable and you might be surprised at what I found. Check out the eBook Eliminate the Production Programming Frustrations.
