The ScanWorks Fast Flash Programming (FFP) action—whether executed through a SPI Flash Player Instrument or a Short Scan Chain Instrument—is powered by an FPGA configuration created with the ScanWorks Embedded Technology Generator (ETG) support application. Using ETG, a customized FPGA configuration is generated, incorporating a user-provisioned instrument dedicated to FFP functionality.
Customers leveraging FFP to significantly accelerate flash programming may also need additional capabilities to facilitate the proper operation of their boards, prior to flashing, such as managing power-up sequences, to ensure proper board initialization. Through service efforts with ASSET InterTech, a hybrid solution can be developed that includes both the ASSET Fast Flash Programming Instrument and customer-specific intellectual property (IP). This blog explores the process of integrating customer IP into an FPGA configuration generated by the ETG support application.
The following illustration presents an FPGA top-level module generated by ASSET InterTech’s ETG application. This module instantiates a Fast Flash Programming Instrument (in blue) and two customer IP modules (in green). All components are accessible through Boundary Scan Registers (depicted as orange squares) via the boundary scan chain. The scan chain is controlled by the FPGA Test Access Point (TAP) controller—a vendor-specific module configured for the target FPGA and instantiated int the device by ETG.
ASSET’s ScanWorks tool suite facilitates the Fast Flash Programming (FFP) action through an ASSET InterTech Hardware Controller connected to the board’s JTAG port. Customer IP can be accessed via boundary scan registers linked to module ports using ScanWorks’ macro actions, provided control or status retrieval is required. Alternatively, if the included customer IP can function autonomously—such as through a sequencer or state machine—and does not require status queries, it may not need to be connected to the boundary scan chain.
A sequence in ScanWorks can be created by the user to ensure the actions are executed in the correct order. For example, an initial macro action might initiate the board’s power-on procedure, bringing the Flash memory attached to the FPGA online. Subsequently, an FFP action can then be performed successfully.
The integration of customer IP into a ScanWorks-generated FPGA configuration offers an effective way for ASSET InterTech to enhance convenience and flexibility in achieving the desired board-level testing goals. By combining ASSET tools and services offered by ASSET InterTech to incorporate customer IP, we can offer a customized solution that maximizes both efficiency and performance in FPGA configurations. Contact our ASSET InterTech applications engineers if you have custom IP that you would like to have integrated into an FPGA configuration that implements our Fast Flash Programming technology.
For more information and to see FFP in action, check out our video on Fast Flash Programming using FPGA IP. And keep an eye out for the second part of this blog topic where we’ll flip the script and explore instantiating ASSET InterTech’s FFP instrument into customer IP.
Stay tuned for more updates as we continue to expand our support and capabilities, helping you design better and faster with ASSET InterTech.
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