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Category: Arium Probes | SourcePoint™

A Trio of Webinars on x86 JTAG-based Debugging

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Alan Sguigna
For each of the months of January, February and March, I did a webinar on JTAG-based debugging. Since each of the video recordings are about 45 minutes long, I thought it would be helpful to point out the highlights of each, if you don’t have time to sit through the full durations. At the risk of sounding immodest, there are some real gems of information within the demos of each webinar.

Webinar: Embedded @Scale JTAG-based Debug of x86 Servers

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Alan Sguigna
Beginning with Microsoft Azure's Project Olympus, and now a standard within the Open Compute Project, many datacenter servers are now optionally equipped with hardware connectivity between the platform BMC and CPU scan chain. The BMC can thus act as an autonomous JTAG-based embedded out-of-band debug agent, provide low-level triage of system events, such as crashes and hangs. Other use cases, such as hardware validation, manufacturing test, and forensics telemetry are also enabled by this technology.

Webinar: Intel Architectural Event Trace

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Alan Sguigna
Don't miss it! ASSET's Alan Sguigna (that's me), in collaboration with the UEFI Forum, will be presenting and demonstrating SourcePoint using the Intel Architectural Event Trace (AET) feature, which offers an unparalleled level of insight into x86 event generation and code execution.

The UP Squared Chronicles Episode 3: Intel Processor Trace

Picture of Alan Sguigna
Alan Sguigna
Wow! It has been a while. I wrote Episode 2 of my open-source explorations into the AAEON Intel Apollo Lake-based Up Squared board back on June 7th. In that episode, I gave directions on how to build the UEFI debug image for the board, complete with source/symbols for consumption by JTAG debuggers like SourcePoint. In this episode, I show source-level debug with SourcePoint, and take advantage of Intel Processor Trace on the board.

Coding to the SED API: Part 1

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Alan Sguigna
In my UEFI Forum webinar, I demonstrated a utility function for stressing PCI Express ports at-scale using JTAG. Let’s walk through the source code and see how it works under the hood.

Debugging Intel CATERR using Embedded ITP

Picture of Alan Sguigna
Alan Sguigna
In my webinar with the UEFI Forum, I demonstrated some of the utility of using JTAG functionality within BMCs to perform out-of-band debug. This is a tutorial on the coding practices to use the SED API.

PCI Express LTSSM stress using BMC-based Embedded JTAG/ITP

Picture of Alan Sguigna
Alan Sguigna
This past week, I did a webinar in collaboration with the UEFI Forum on JTAG-based UEFI Debug and Trace. This reviewed some of the often-used tools for low-level triage of difficult-to-diagnose, intermittent bugs. Near the end, I demonstrated the usage of technology running directly down on a BMC to perform low-level functions not achievable with firmware or OS-based applications.
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