Boundary Scan Archives | Page 4 of 14

Webinar: Chiplet interconnect testing using JTAG/boundary scan

Alan Sguigna

November 1, 2020
1:32 pm

Join our webinar on Chiplet interconnect testing using JTAG/boundary scan. Hope to meet you then!

Test Generation for “Chiplet”-based, Multi-die Devices Is Now Possible with ScanWorks

Michael Johnson

June 24, 2020
1:28 pm

Since its inception, ScanWorks has provided board-level shorts and opens testing of interconnects between Boundary-Scan devices through use of its Automatic Test Pattern Generation (ATPG) feature. ScanWorks ATPG creates the patterns necessary for shorts and opens testing based on the board topology (i.e. connections between devices) and the Boundary-Scan Cell types on the I/O pins within each device. With recent enhancements, ScanWorks can now generate patterns that can be applied by chip-level automatic test equipment (ATE) to test for shorts and opens in the interconnections between silicon “chiplets” in multi-die devices.

It’s JTAG’s 30th Anniversary!

Alan Sguigna

February 15, 2020
3:29 pm

Today, February 15th, 2020, marks the official 30th Anniversary of JTAG. What a wild ride it has been – from its humble beginnings for detecting short and open circuits, it has evolved to be, in some ways, the most powerful and feared technology on the planet. How did we get here?

ASSET Autotestcon update and some BIG news….

Glenn Woppman

August 28, 2019
3:01 pm

ASSET is at Autotestcon this week meeting with all our defense and avionics customers, both defense contractors and DoD.

Rediscovering the Wonder of JTAG

Alan Sguigna

June 30, 2019
4:22 pm

JTAG is coming up on its 30th anniversary. And some would say it’s older than that. As I prepared for doing an introductory presentation on this amazing technology, I got a chance to reflect on how useful it has become, and what the next 30 years might be like.

JTAG Testing of the i.MX6 SABRE Lite Board

Alan Sguigna

April 22, 2019
6:08 am

ASSET recently released an enhanced product for testing i.MX6-based board designs using JTAG. I fired up this new tool on the Boundary Devices SABRE Lite board, with some fun and interesting results.

Unboxing Boundary-Scan Test Part 4: Detecting Fault Injection with SPV

Alan Sguigna

March 3, 2019
4:41 pm

In Part 3 of this series, I looked at the JTAG scan path of the ASSET ScanLite demo board, and explored some of the fundamentals of IEEE 1149.1. This week, I do some fault insertion on the scan path, and see how that is detected by boundary scan.

Unboxing Boundary-Scan Test Part 3: More on Scan Path Verify

Alan Sguigna

February 10, 2019
2:13 pm

In the last blog, I explored the JTAG scan path of the ScanLite demonstration board. In this article, I do a deeper dive into what options are available within ScanWorks to verify the scan path, and explore some of the underlying technology of IEEE 1149.1.

Unboxing Boundary-Scan Test Part 2: Scan Path Verify

Alan Sguigna

January 6, 2019
2:24 pm

This week, I looked at some of the main test actions that apply to the ScanLite board: in particular, the Scan Path Verify action.

Unboxing Boundary-Scan Test

Alan Sguigna

December 16, 2018
8:26 pm

I’ve gotten all of my Christmas shopping done early, so I managed to make some time for exploring our ScanWorks test tool. I’m taking a “newbie approach” to using the tool, initially for hacking around with boundary-scan test. There’s some pretty cool technology here.

Category: Boundary Scan

Webinar: Chiplet interconnect testing using JTAG/boundary scan

Test Generation for “Chiplet”-based, Multi-die Devices Is Now Possible with ScanWorks

It’s JTAG’s 30th Anniversary!

ASSET Autotestcon update and some BIG news….

Rediscovering the Wonder of JTAG

JTAG Testing of the i.MX6 SABRE Lite Board

Unboxing Boundary-Scan Test Part 4: Detecting Fault Injection with SPV

Unboxing Boundary-Scan Test Part 3: More on Scan Path Verify

Unboxing Boundary-Scan Test Part 2: Scan Path Verify

Unboxing Boundary-Scan Test

Archives

Categories