Boundary Scan Archives | Page 7 of 14

Embedded Boundary Scan for Defense Systems

Alan Sguigna

June 21, 2017
11:18 am

ASSET was recently awarded a multi-year contract for embedding boundary-scan test technology within a military system design. This meets a requirement of greater than 92% structural test diagnostic accuracy in-system, and will save millions of dollars over the lifespan of the system.

At-speed SPI Flash/EEPROM Programming using FPGA and JTAG – Revised

Michael Johnson

June 21, 2017
9:53 am

At-Scale Test

Alan Sguigna

April 30, 2017
1:32 pm

Now that At-Scale Debug (ASD) is becoming a de facto standard on Intel designs for the remote execution of CScripts, what other applications can take advantage of this technology?

ASSET and CCI collaborate on integrated test solutions

Alan Sguigna

January 17, 2017
8:10 pm

Combining boundary-scan structural test with functional test is a “best practice” approach to high test coverage at least cost. So, it only makes sense that ASSET collaborates with Circuit Check.

NBT at the BTW

Alan Sguigna

September 18, 2016
4:12 pm

ASSET’s Michael Johnson presented an update on Non-intrusive Board Test (NBT) at the 13th Annual Board Test Workshop (BTW) in Fort Collins, CO this past week. The overall question posed at the Workshop was, “Is Board Test Losing Relevance”?

Boundary-Scan Test on the TI MSP430

Alan Sguigna

September 5, 2016
1:53 pm

The MSP430 is a mixed-signal microcontroller family from Texas Instruments. Built around a 16-bit CPU, the MSP430 is designed for low cost, low power consumption embedded applications. But, does it support boundary scan for board test purposes?

Using Boundary-Scan Test at Debug & Repair Stations

Alan Sguigna

August 14, 2016
3:06 pm

Is it possible to use JTAG at debug & repair depots to reduce the cost of diagnosing bad boards?

JTAG and IJTAG-based Fast Flash Programming Algorithms

Alan Sguigna

March 20, 2016
5:11 pm

In recent years, the increasing size of flash memory has driven device programming to offline methods. However, new techniques are significantly reducing in-system programming times, making it much more feasible and convenient to program flash memory after it’s already been soldered to the board.

High Availability within Software-Defined Networks

Alan Sguigna

September 27, 2015
5:48 pm

As network functions become virtualized and proprietary hardware migrates to commodity Intel-based servers, will Carrier service levels degrade?

JTAG|DDR4 Connectivity Test Mode (JESD79-4)

Kent Zetterberg

September 22, 2015
2:45 pm

Recently launched DDR4 devices have what memory device vendors may refer to as a “boundary scan” test mode. Even though there’s not really a boundary-scan function involved on the DDR4 side, this mode actually has been, as claimed by JEDEC, “designed to work seamlessly with any boundary-scan devices.” Here’s a brief introduction to what it does and how to test it with a boundary-scan (JTAG) tool.

Category: Boundary Scan

Embedded Boundary Scan for Defense Systems

At-speed SPI Flash/EEPROM Programming using FPGA and JTAG – Revised

At-Scale Test

ASSET and CCI collaborate on integrated test solutions

NBT at the BTW

Boundary-Scan Test on the TI MSP430

Using Boundary-Scan Test at Debug & Repair Stations

JTAG and IJTAG-based Fast Flash Programming Algorithms

High Availability within Software-Defined Networks

JTAG|DDR4 Connectivity Test Mode (JESD79-4)

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