We know that the board bring-up process can be extremely challenging on today’s complex, high-speed designs. How do we get the iterative validation, test and debug steps off of the critical path of new product introduction?
A customer shared some empirical results from boundary-scan testing of the Intel QuickPath Interconnect (QPI) nets on their design. These nets cannot be covered using In-Circuit Test (ICT), and some short-circuit and open-circuit defects defy detection using conventional functional test. What did they find?
Boundary scan is known to be quite slow to program large flash devices. But, with a new approach using SPI Master IP within an FPGA, flash programming time can be decreased by a factor of 15 or more.
