Category: High-Speed I/O

Video recording of Chiplet interconnect test webinar

Alan Sguigna

December 3, 2020
5:14 pm

In case you missed it, a recording of Michael Johnson's webinar, Chiplet Interconnect Testing using JTAG/Boundary Scan, is now available. Click on the link, and enjoy the show.

Defense contractor uses ScanWorks PFx tool to solve tough DDR problem in Zynq-7000 design

Larry Osborn

July 23, 2019
1:57 pm

I get excited whenever we have an opportunity to assist the defense community with engineering challenges, whether those challenges are in the form of hardware or software, design or manufacturing.

Advanced support for Teradyne HSSub PXIe systems

Alan Sguigna

September 11, 2017
7:48 am

We announced today the extended integration of ScanWorks’ boundary-scan test capabilities with the Teradyne’s PXI Express-based High Speed Subsystem (HSSub). Come see a demo at Booth #101 at the AUTOTESTCON conference!

At-Scale Test

Alan Sguigna

April 30, 2017
1:32 pm

Now that At-Scale Debug (ASD) is becoming a de facto standard on Intel designs for the remote execution of CScripts, what other applications can take advantage of this technology?

Using Embedded Run-Control for PCIe Link Testing – Part 2

Alan Sguigna

December 4, 2016
11:19 pm

In my last blog, I referred to the use of run-control technology to very quickly exercise the PCI Express link training state machine. What other kinds of tests can be run with this approach?

Using Embedded Run-Control for PCIe Link Training Testing

Alan Sguigna

November 6, 2016
5:43 pm

It is often part of a hardware validation test suite to initiate multiple PCIe bus retrains, looking for hardware design issues, or LTSSM RTL bugs in the device under test. These test suites take a very long time to run. Is there a way to speed them up?

Data Mining Analytics Improves Serdes HSIO Validation

Tim Caffee

October 7, 2015
1:12 pm

A new era and new insight – Real Insight

Glenn Woppman

July 13, 2015
1:21 pm

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Glenn Woppman

December 9, 2014
11:30 am

Memory Training, Testing, and Margining

Alan Sguigna

November 2, 2014
3:38 pm

What happens during DDR memory training/initialization, and how does it differ from what is needed for manufacturing testing or system marginality validation?

Category: High-Speed I/O

Video recording of Chiplet interconnect test webinar

Defense contractor uses ScanWorks PFx tool to solve tough DDR problem in Zynq-7000 design

Advanced support for Teradyne HSSub PXIe systems

At-Scale Test

Using Embedded Run-Control for PCIe Link Testing – Part 2

Using Embedded Run-Control for PCIe Link Training Testing

Data Mining Analytics Improves Serdes HSIO Validation

A new era and new insight – Real Insight

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Memory Training, Testing, and Margining

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