High-Speed I/O Archives | Page 2 of 10

Avoiding stitching vias and decoupling capacitors on high-speed signals

Alan Sguigna

September 17, 2014
2:46 pm

Is it possible to bend, but not break, some time-honored board design guidelines to reduce board cost, but still maintain signal integrity?

JTAG | one TAP, many non-intrusive apps

Adam Ley

September 9, 2014
12:42 pm

The origins of JTAG are inextricably bound up with boundary scan. Yet, it provides many capabilities to many purposes. Often, as part of a point tool, whether for debug, programming, test or validation, it takes on just one capability. But, no matter the purpose, as the thread common to all, the standard Test Access Port (TAP) opens the way for many applications. In the test domain, several of these unite under the banner Non-intrusive Board Test (NBT).

Single Stripline versus Dual Stripline, and Board Routing

Alan Sguigna

August 17, 2014
2:00 pm

In the previous blog on PCB Insertion Loss and High-Speed Buses, we described how this loss increases with greater link speed. Designing for higher link speeds may, as a consequence, drive up PCB cost. This blog explains some techniques to mitigate this cost increase.

PCB Insertion Loss and High-Speed Buses

Alan Sguigna

July 27, 2014
3:54 pm

As high-speed differential buses on today’s board designs become faster, the maximum allowable PCB insertion loss declines. What causes this effect, and how can it be mitigated?

DDR Testing using Spoofed Memory Reference Code – Part 2

Alan Sguigna

July 20, 2014
3:42 pm

In Part 1 of this blog, we discussed some of the limitations of ICT, boundary-scan, and conventional functional test for testing memories. This Part 2 reviews methodologies that overcome these constraints.

DDR Testing using Spoofed Memory Reference Code – Part 1

Alan Sguigna

July 13, 2014
2:55 pm

Off-the-shelf memory initialization routines typically do not provide the needed diagnostic resolution if a structural failure causes the system to “blue screen”. How can test engineers overcome this?

DDR Crosstalk Analysis using Margining Technologies

Alan Sguigna

June 22, 2014
8:02 pm

In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?

PCI Express 4.0, Retimers, and Trace Length

Alan Sguigna

June 15, 2014
4:39 pm

At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?

Bit Error Rate of Intel QuickPath Interconnect – Part 2

Alan Sguigna

June 8, 2014
4:34 pm

In a previous blog, we touched on some of the key attributes of Intel QuickPath Interconnect versus PCI Express Gen3, to explain why the acceptable bit error rate threshold of Intel QPI is two orders of magnitude lower. This article elaborates on how some of the key design features of QPI contribute to this more stringent requirement.

Common SATA Signal Integrity Issues

Alan Sguigna

June 1, 2014
1:43 pm

Serial ATA (SATA)-based systems come in a wide range of topologies and trace/cable lengths. This presents signal integrity challenges due to signal loss, reflection and crosstalk; causing SATA device detection problems, lack of interoperability, slower performance, and increased radio frequency interference. What are the main issues, and how do designers mitigate them?

Category: High-Speed I/O

Avoiding stitching vias and decoupling capacitors on high-speed signals

JTAG | one TAP, many non-intrusive apps

Single Stripline versus Dual Stripline, and Board Routing

PCB Insertion Loss and High-Speed Buses

DDR Testing using Spoofed Memory Reference Code – Part 2

DDR Testing using Spoofed Memory Reference Code – Part 1

DDR Crosstalk Analysis using Margining Technologies

PCI Express 4.0, Retimers, and Trace Length

Bit Error Rate of Intel QuickPath Interconnect – Part 2

Common SATA Signal Integrity Issues

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