High-Speed I/O Archives | Page 5 of 10

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV)

Alan Sguigna

April 23, 2013
1:57 pm

Back a few years ago, engineers used expensive high-end oscilloscopes to perform signal integrity validation (SIV) on their designs, and considered that adequate in determining the success of a design. But with today’s products, process and parameter variations occur that require system marginality validation (SMV) to be done by less expensive software-based tools, to determine if a design is ready for high volume production.

Defects on High-Speed Memory

Alan Sguigna

April 7, 2013
12:00 pm

In previous blogs we covered the kind of defects that might exist on high-speed serial I/O and their associated impacts on system performance and stability. A similar analysis on DDR SDRAM yields some interesting findings.

Structural Defects on High-Speed Serial I/O – Part 3

Alan Sguigna

March 31, 2013
1:51 pm

In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.

Structural Defects on High-Speed Serial I/O – Part 2

Alan Sguigna

March 24, 2013
6:04 pm

In my previous blog, we reviewed the effects of a missing capacitor and a short to ground on the performance of high-speed serial buses. What other kinds of defects should be considered, and what can we do about them?

Adaptive Equalization and Power Consumption

Alan Sguigna

March 10, 2013
10:25 am

Poorly tuned adaptive equalization will cause systems to gulp power, instead of sipping it. What’s the technology behind this?

Structural Defects on High-Speed Serial I/O

Alan Sguigna

March 2, 2013
4:13 pm

Shorts and open circuits on high-speed serdes buses, such as PCI Express, may have subtle and difficult-to-diagnose effects on system performance. In other words, you might not know about them until customers start complaining and you get warranty returns. What kind of effects are these, and how are they prevented?

DDR4, Signal Integrity, and Power Integrity

Alan Sguigna

February 24, 2013
2:53 pm

One of the biggest design challenges today revolves around maintaining signal integrity in the presence of power and ground rail fluctuations due to simultaneously switching signals. This is particularly true for DDR4 memory.

Signal Integrity Margins of different DIMM Suppliers

Alan Sguigna

February 9, 2013
4:05 pm

Not all memories are created equal. Some DIMM suppliers’ cards have margins that are better than others. And of course, the better the margins, the better the performance of the system, and the fewer blue screens.

How to avoid poor serdes performance caused by circuit board manufacturing variances

Eric Johnson

February 8, 2013
8:24 am

The Intel Cougar Point SATA Bug

Alan Sguigna

January 26, 2013
1:48 pm

In early 2011, Intel discovered a design issue on their Cougar Point chipset, and took an approximately $700 million charge against earnings to repair and replace affected parts and systems. What may have been the root cause of this, and how may it have been prevented?

Category: High-Speed I/O

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV)

Defects on High-Speed Memory

Structural Defects on High-Speed Serial I/O – Part 3

Structural Defects on High-Speed Serial I/O – Part 2

Adaptive Equalization and Power Consumption

Structural Defects on High-Speed Serial I/O

DDR4, Signal Integrity, and Power Integrity

Signal Integrity Margins of different DIMM Suppliers

How to avoid poor serdes performance caused by circuit board manufacturing variances

The Intel Cougar Point SATA Bug

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