Category: High-Speed I/O

Margins (Eye Diagrams) follow the Silicon – Part 2

Alan Sguigna

January 20, 2013
10:17 am

In my previous blog I covered at a high level why system signal integrity is highly dependent upon the silicon. Let’s dive into this a little deeper by first looking at wafer and die manufacturing variances.

Signal Integrity testing with CRCs versus pattern generation and capture

Alan Sguigna

January 9, 2013
4:45 pm

I was asked recently whether engineers could just check the CRC error counts coming from the Operating System to ensure they had good signal integrity and operating margins. After all, a CRC checks for bit errors, right? Here’s why this is not good enough:

Margins (Eye Diagrams) follow the Silicon

Alan Sguigna

December 9, 2012
8:07 pm

We know from empirical evidence that a system’s operating margins are as sensitive to the chips on the board, as they are to the board’s design and manufacturing process itself. Why is this so?

Adaptive Equalization – Part 2

Alan Sguigna

December 2, 2012
11:56 am

In a previous blog, I described how fixed and adaptive equalization techniques are used within chips to ensure signal integrity even in adverse system conditions. Why is it important to tune these parameters within a chip?

PRBS31 and Validation of High-Speed SerDes

Alan Sguigna

November 11, 2012
8:40 pm

What’s the right dwell time, or pattern length, to consider when checking for intersymbol interference, clock recovery, and circuit drift?

Adaptive Equalization, or “The Math is in the Chip”

Alan Sguigna

November 2, 2012
12:38 pm

Modern high-speed I/O equalization schemes typically include both fixed (programmable) and adaptive components to ensure signal integrity even in adverse system conditions. What tools are available to ensure that these equalization techniques are working properly on a given system?

Single-bit Memory Errors

Alan Sguigna

October 24, 2012
4:23 pm

Ever wonder if a stray cosmic ray or alpha particle might double your bank account, due to an undetected RAM error?

Oscilloscopes versus Embedded Instruments

Alan Sguigna

October 7, 2012
8:33 pm

What’s cheaper, faster, and more powerful than an oscilloscope, when it comes to validating high-speed signal integrity? Why, a software application using embedded instruments, of course. How is this possible?

Testing Intel Sandy Bridge and Ivy Bridge

Alan Sguigna

September 30, 2012
2:24 pm

In my last few blogs, I’ve talked about the challenges of testing QPI, PCI Express, SATA 3, and DDR3 memory. These buses are common to many Intel Sandy Bridge and Ivy Bridge motherboard designs. Should test engineers take chances and just not test them?

Testing SATA 3

Alan Sguigna

September 9, 2012
2:27 pm

Serial ATA 3 (SATA 3, or SATA III) is a differential bus running at 6Gbps. It’s commonly used on computer motherboards, such as notebooks, to connect to mass storage devices. How do you know if your hard disk or flash drive is running at full speed?

Category: High-Speed I/O

Margins (Eye Diagrams) follow the Silicon – Part 2

Signal Integrity testing with CRCs versus pattern generation and capture

Margins (Eye Diagrams) follow the Silicon

Adaptive Equalization – Part 2

PRBS31 and Validation of High-Speed SerDes

Adaptive Equalization, or “The Math is in the Chip”

Single-bit Memory Errors

Oscilloscopes versus Embedded Instruments

Testing Intel Sandy Bridge and Ivy Bridge

Testing SATA 3

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