High-Speed I/O Archives | Page 9 of 10

PCT Detects Link Training Failures

Alan Sguigna

August 8, 2011
10:47 am

One of our customers was experiencing field returns when 10 Gigabit Ethernet ports started failing to pass traffic at full line rate. How could they test for these failing boards in manufacturing and prevent them from getting out to customers?

Board Bring-Up

Alan Sguigna

July 17, 2011
4:28 pm

Board bring up of an early prototype is one of the most important steps for a design team. The first boards must pass through a battery of tests to demonstrate that the hardware is rock-solid. Non-intrusive technologies can be used to accelerate this process.

Drift in High-Speed I/O Circuits

Alan Sguigna

June 12, 2011
5:45 pm

With chip-to-chip interconnects now running at 8 GT/s and above, a new class of faults due to manufacturing and process drift is emerging. What are these faults and how are they detected?

The Experts weigh in on Serial-Data Link Testing

Alan Sguigna

May 14, 2011
4:49 pm

Today I read an interesting article in Electronic Design magazine about the complexity of testing third-generation serial-data technology. With comments from Agilent, Tektronix and LeCroy, the article highlights all of the problems associated with oscilloscopes, BERTs, AWGs and other “heavy-metal” products, and not surprisingly doesn’t say anything about the elegant alternative of using embedded instrumentation…

The Limitations of ICT

Alan Sguigna

April 9, 2011
2:58 pm

Tired of that old bed-of-nails? Legacy In-Circuit Test (ICT) has been diminishing in value for a long time. Let’s explore some of the current technical issues with ICT as test access on new circuit board designs continues to disappear.

The test stack

Alan Sguigna

February 20, 2011
9:20 am

Those of you with a telecom background are no doubt aware of the “OSI Network Model”, also known as the OSI pyramid or stack. It is a way of sub-dividing a communications system into smaller parts called layers. A layer is a collection of similar functions that provide services to the layer above it and receives services from the layer below it. A decade ago, the telecommunications test industry underwent a revolution when platforms emerged that could cover multiple layers of the OSI stack. Now, the same thing is happening in the circuit board test industry...

Testing 2nd generation Intel® Core™ microarchitecture (aka Sandy Bridge)

Alan Sguigna

January 17, 2011
4:16 pm

Some of you may have noticed Intel’s announcement this past week at CES of the new generation of desktop/mobile processors, the 2nd Generation Intel Core family. These processors are based upon a new microarchitecture at a 32nm process node. This increased level of density and functionality requires new board testing strategies...

Hope is not a strategy…

Glenn Woppman

December 17, 2010
11:45 am

The world of validation has changed dramatically over the last few years due to the added challenge of increasing bus speeds. My observation across the industry is there are two camps companies are aligning on...

High Speed I/O Testing on In-Circuit Test

Alan Sguigna

November 4, 2010
6:19 pm

Because ASSET is a pioneer in the use of non-intrusive solutions for validation, test and debug (using what we call “embedded instrumentation”), we often get asked if legacy testers like In-Circuit Test (ICT) machines can be used for the testing of high-speed I/O...

Category: High-Speed I/O

PCT Detects Link Training Failures

Board Bring-Up

Drift in High-Speed I/O Circuits

The Experts weigh in on Serial-Data Link Testing

More Problems with In-Circuit Test

The Limitations of ICT

The test stack

Testing 2nd generation Intel® Core™ microarchitecture (aka Sandy Bridge)

Hope is not a strategy…

High Speed I/O Testing on In-Circuit Test

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