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Test Generation for “Chiplet”-based, Multi-die Devices Is Now Possible with ScanWorks

Michael Johnson

June 24, 2020
1:28 pm

Since its inception, ScanWorks has provided board-level shorts and opens testing of interconnects between Boundary-Scan devices through use of its Automatic Test Pattern Generation (ATPG) feature. ScanWorks ATPG creates the patterns necessary for shorts and opens testing based on the board topology (i.e. connections between devices) and the Boundary-Scan Cell types on the I/O pins within each device. With recent enhancements, ScanWorks can now generate patterns that can be applied by chip-level automatic test equipment (ATE) to test for shorts and opens in the interconnections between silicon “chiplets” in multi-die devices.

It’s JTAG’s 30th Anniversary!

Alan Sguigna

February 15, 2020
3:29 pm

Today, February 15th, 2020, marks the official 30th Anniversary of JTAG. What a wild ride it has been – from its humble beginnings for detecting short and open circuits, it has evolved to be, in some ways, the most powerful and feared technology on the planet. How did we get here?

ASSET named one of 50 most trustworthy technology companies for 2019

Alan Sguigna

September 18, 2019
1:54 pm

The endorsements keep coming: in addition to recently winning the "Walter E. Peterson Best Paper on New Technology", we were just named one of the 50 Most Trustworthy Companies for 2019 by Silicon Review magazine.

Using JTAG for Silicon Trojan Detection and Mitigation

Alan Sguigna

September 1, 2019
11:53 am

This past week, I attended the AUTOTESTCON 2019 conference, the premiere Defense Automated Test Equipment show, that has the theme of “increased mission effectiveness through advanced test and support technology”. As you may have seen, I was honored with the “Walter E. Peterson Best Paper on New Technology” award for Mitigating JTAG as an Attack Surface (note: it might take a little while for the paper to be posted on IEEE Xplore; you might have to check back later).

Securing the JTAG Interface

Alan Sguigna

July 21, 2019
4:10 pm

In a prior blog, I wrote about the JTAG specification’s upcoming 30th anniversary, and reflected on how it has evolved over the years, and the powerful use cases it can be put to. This week, we look at how to secure the JTAG interface, to prevent its abuse by bad actors.

Unboxing Boundary-Scan Test Part 4: Detecting Fault Injection with SPV

Alan Sguigna

March 3, 2019
4:41 pm

In Part 3 of this series, I looked at the JTAG scan path of the ASSET ScanLite demo board, and explored some of the fundamentals of IEEE 1149.1. This week, I do some fault insertion on the scan path, and see how that is detected by boundary scan.

Unboxing Boundary-Scan Test Part 3: More on Scan Path Verify

Alan Sguigna

February 10, 2019
2:13 pm

In the last blog, I explored the JTAG scan path of the ScanLite demonstration board. In this article, I do a deeper dive into what options are available within ScanWorks to verify the scan path, and explore some of the underlying technology of IEEE 1149.1.

A Father/Son Cryptocurrency Mining Rig Project

Alan Sguigna

February 25, 2018
8:18 pm

A few months ago, my son began to take an interest in cryptocurrency, and we decided to build an Ethereum mining rig together. But it wasn’t as easy to do as it seemed it would be at first.

JTAG Master function for embedded debug and test

Alan Sguigna

December 10, 2017
4:49 pm

In my last article, I described how the Open Compute Project (OCP) Project Olympus server designs have been put into the public domain by Microsoft Azure. Inherent in the Olympus servers is the hardware connection between the ASPEED BMC and the CPU JTAG chain. To make the most of this connection for hardware-assisted debug and test purposes, a high-performance, secure JTAG Master function is needed within the BMC.

Locks, Keys and Traps: Securing device JTAG interfaces

Alan Sguigna

July 10, 2017
5:57 pm

In two previous articles, I looked at the JTAG access port from a security perspective, and considered what exposure the choice of BMC operating system might have on a platform supporting At-Scale Debug. Now, let’s consider the root of all trust, the silicon itself, and see what options exist for locking it down.

Category: Industry Standards and Forums

Test Generation for “Chiplet”-based, Multi-die Devices Is Now Possible with ScanWorks

It’s JTAG’s 30th Anniversary!

ASSET named one of 50 most trustworthy technology companies for 2019

Using JTAG for Silicon Trojan Detection and Mitigation

Securing the JTAG Interface

Unboxing Boundary-Scan Test Part 4: Detecting Fault Injection with SPV

Unboxing Boundary-Scan Test Part 3: More on Scan Path Verify

A Father/Son Cryptocurrency Mining Rig Project

JTAG Master function for embedded debug and test

Locks, Keys and Traps: Securing device JTAG interfaces

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