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JTAG Master function for embedded debug and test

Alan Sguigna

December 10, 2017
4:49 pm

In my last article, I described how the Open Compute Project (OCP) Project Olympus server designs have been put into the public domain by Microsoft Azure. Inherent in the Olympus servers is the hardware connection between the ASPEED BMC and the CPU JTAG chain. To make the most of this connection for hardware-assisted debug and test purposes, a high-performance, secure JTAG Master function is needed within the BMC.

Locks, Keys and Traps: Securing device JTAG interfaces

Alan Sguigna

July 10, 2017
5:57 pm

In two previous articles, I looked at the JTAG access port from a security perspective, and considered what exposure the choice of BMC operating system might have on a platform supporting At-Scale Debug. Now, let’s consider the root of all trust, the silicon itself, and see what options exist for locking it down.

ASSET attends the Open Compute Summit

Alan Sguigna

March 9, 2017
8:57 pm

I spent the past two days at the Open Compute Project (OCP) U.S. Summit 2017, in Santa Clara, California. The HUGE news is that Microsoft has ported Windows Server to ARMv8 chips from Qualcomm and Cavium (but, for now, only for use within Azure).

2016 UEFI Forum Plugfest – Seattle, WA

Alan Sguigna

September 25, 2016
4:09 pm

ASSET (yours truly) attended the September 2016 Plugfest at the UEFI Forum in Seattle, WA. Was it worthwhile?

NBT at the BTW

Alan Sguigna

September 18, 2016
4:12 pm

ASSET’s Michael Johnson presented an update on Non-intrusive Board Test (NBT) at the 13th Annual Board Test Workshop (BTW) in Fort Collins, CO this past week. The overall question posed at the Workshop was, “Is Board Test Losing Relevance”?

Boundary-Scan Test on the TI MSP430

Alan Sguigna

September 5, 2016
1:53 pm

The MSP430 is a mixed-signal microcontroller family from Texas Instruments. Built around a 16-bit CPU, the MSP430 is designed for low cost, low power consumption embedded applications. But, does it support boundary scan for board test purposes?

Benefits of, and Misconceptions about, UEFI

Alan Sguigna

May 8, 2016
4:42 pm

ASSET recently joined the UEFI Forum and, enjoying the benefits of membership, we came across this paper extolling the virtues of the technology and clarifying some common misconceptions.

ASSET Joins the UEFI Forum

Alan Sguigna

March 27, 2016
4:04 pm

As the UEFI Forum continues to make advances in the technology behind what is still called the BIOS (Basic Input/Output System), ASSET has joined this standards body to assist in the debug of its latest features.

IJTAG vs JTAG vs IEEE 1500 ECT

John Potter

February 24, 2016
8:50 am

Control Plane and Data Plane Management of Next-Gen ASICs

Alan Sguigna

November 1, 2015
4:39 pm

As new devices emerge supporting the new Software-Defined Networking standards, what debug challenges await design engineers?

Category: Industry Standards and Forums

JTAG Master function for embedded debug and test

Locks, Keys and Traps: Securing device JTAG interfaces

ASSET attends the Open Compute Summit

2016 UEFI Forum Plugfest – Seattle, WA

NBT at the BTW

Boundary-Scan Test on the TI MSP430

Benefits of, and Misconceptions about, UEFI

ASSET Joins the UEFI Forum

IJTAG vs JTAG vs IEEE 1500 ECT

Control Plane and Data Plane Management of Next-Gen ASICs

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