Category: Intel® IBIST

Using Embedded Run-Control for PCIe Link Testing – Part 2

Alan Sguigna

December 4, 2016
11:19 pm

In my last blog, I referred to the use of run-control technology to very quickly exercise the PCI Express link training state machine. What other kinds of tests can be run with this approach?

A new era and new insight – Real Insight

Glenn Woppman

July 13, 2015
1:21 pm

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Glenn Woppman

December 9, 2014
11:30 am

Memory Training, Testing, and Margining

Alan Sguigna

November 2, 2014
3:38 pm

What happens during DDR memory training/initialization, and how does it differ from what is needed for manufacturing testing or system marginality validation?

Single Stripline versus Dual Stripline, and Board Routing

Alan Sguigna

August 17, 2014
2:00 pm

In the previous blog on PCB Insertion Loss and High-Speed Buses, we described how this loss increases with greater link speed. Designing for higher link speeds may, as a consequence, drive up PCB cost. This blog explains some techniques to mitigate this cost increase.

PCB Insertion Loss and High-Speed Buses

Alan Sguigna

July 27, 2014
3:54 pm

As high-speed differential buses on today’s board designs become faster, the maximum allowable PCB insertion loss declines. What causes this effect, and how can it be mitigated?

DDR Testing using Spoofed Memory Reference Code – Part 1

Alan Sguigna

July 13, 2014
2:55 pm

Off-the-shelf memory initialization routines typically do not provide the needed diagnostic resolution if a structural failure causes the system to “blue screen”. How can test engineers overcome this?

DDR Crosstalk Analysis using Margining Technologies

Alan Sguigna

June 22, 2014
8:02 pm

In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?

PCI Express 4.0, Retimers, and Trace Length

Alan Sguigna

June 15, 2014
4:39 pm

At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?

Bit Error Rate of Intel QuickPath Interconnect – Part 2

Alan Sguigna

June 8, 2014
4:34 pm

In a previous blog, we touched on some of the key attributes of Intel QuickPath Interconnect versus PCI Express Gen3, to explain why the acceptable bit error rate threshold of Intel QPI is two orders of magnitude lower. This article elaborates on how some of the key design features of QPI contribute to this more stringent requirement.

Category: Intel® IBIST

Using Embedded Run-Control for PCIe Link Testing – Part 2

A new era and new insight – Real Insight

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Memory Training, Testing, and Margining

Single Stripline versus Dual Stripline, and Board Routing

PCB Insertion Loss and High-Speed Buses

DDR Testing using Spoofed Memory Reference Code – Part 1

DDR Crosstalk Analysis using Margining Technologies

PCI Express 4.0, Retimers, and Trace Length

Bit Error Rate of Intel QuickPath Interconnect – Part 2

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