Category: Intel® IBIST

Common SATA Signal Integrity Issues

Alan Sguigna

June 1, 2014
1:43 pm

Serial ATA (SATA)-based systems come in a wide range of topologies and trace/cable lengths. This presents signal integrity challenges due to signal loss, reflection and crosstalk; causing SATA device detection problems, lack of interoperability, slower performance, and increased radio frequency interference. What are the main issues, and how do designers mitigate them?

Bit Error Rate of Intel QuickPath Interconnect – Part 1

Alan Sguigna

April 27, 2014
4:02 pm

The required Bit Error Rate (BER) of Intel® QuickPath Interconnect (QPI) is 1 error in 10E14 bits. The BER threshold of PCI Express is 1 error in 10E12 bits. What might account for the two orders of magnitude difference?

The Statistical Basis of System Marginality Validation (SMV)

Alan Sguigna

March 16, 2014
4:48 pm

Determining the margins of a system requires taking a statistically large-enough data collection sample size to achieve a meaningful result. The sample size takes into account variances due to silicon process, temperature, voltage, finite test time, and a number of other factors. What is the math behind this?

What is Board Bring-Up – Part 2

Alan Sguigna

March 9, 2014
4:09 pm

We know that the board bring-up process can be extremely challenging on today’s complex, high-speed designs. How do we get the iterative validation, test and debug steps off of the critical path of new product introduction?

Structural Defects on Intel QuickPath Interconnect – Part 2

Alan Sguigna

March 2, 2014
1:24 pm

Suppose there’s a hidden short-circuit on an Intel QPI net under the CPU socket – what’s the customer going to see?

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV) – Part 3

Alan Sguigna

February 2, 2014
5:26 pm

In previous blogs, we contrasted the use of oscilloscopes to perform signal integrity validation (SIV) against silicon embedded instruments for system marginality validation (SMV). Why is SMV superior?

Will BIST Kill T&M?

Alan Sguigna

September 29, 2013
5:14 pm

To quote Ransom Stephens in the DesignCon Community Blog, “BIST (Built-In System Test), is an acronym that would keep executives at test-and-measurement companies awake at night, if they knew what it meant.” What’s he talking about?

Silicon Aging and Signal Integrity

Alan Sguigna

August 25, 2013
4:40 pm

Fruit rots. Tires wear out. And silicon ages, too. Let’s look at the degradation process and its effects on chip signal integrity and performance.

Boundary-Scan Testing of DDR3 and DDR4 Memory

Alan Sguigna

July 13, 2013
4:52 pm

In the blog Boundary-Scan Testing of PCI Express, we examined how JTAG can be used to detect structural defects on high-speed serial I/O. Now let’s review the situation for DDR3 and DDR4 memory.

First to support all of Intel® Silicon View Technology

Eric Johnson

June 10, 2013
9:19 am

Category: Intel® IBIST

Common SATA Signal Integrity Issues

Bit Error Rate of Intel QuickPath Interconnect – Part 1

The Statistical Basis of System Marginality Validation (SMV)

What is Board Bring-Up – Part 2

Structural Defects on Intel QuickPath Interconnect – Part 2

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV) – Part 3

Will BIST Kill T&M?

Silicon Aging and Signal Integrity

Boundary-Scan Testing of DDR3 and DDR4 Memory

First to support all of Intel® Silicon View Technology

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