Intel® IBIST Archives | Page 3 of 7

Boundary-Scan Testing of PCI Express

Alan Sguigna

June 9, 2013
9:19 pm

As we’ve covered in some previous blogs, the differential, AC-coupled nature of PCI Express allows this bus to be somewhat self-healing, whereby some structural defects will allow the bus to transparently run, albeit at a degraded performance. Due to this, these short-circuit and open-circuit defects may be completely masked from conventional functional test. But such defects are important to detect, because they will affect the throughput of the port. Boundary scan can be used to detect these defects, subject to the implementation of IEEE 1149.1 and IEEE 1149.6 in the chips.

Defects on High-Speed Memory – Part 2

Alan Sguigna

May 19, 2013
8:37 pm

Last month, we saw how defects on memory data lines can cause a system to fail, and yet escape detection by the system boot loader or BIOS. Let’s examine this in more technical detail.

SIV versus SMV – Part 2

Alan Sguigna

May 5, 2013
12:06 pm

Last week we saw a $300,000 oscilloscope. This week, we look at another one for $470,000. The sky’s the limit when it comes budgeting for ‘scopes. But aside from the price, what other advantages are there of embedded instrumentation-based system marginality validation tools?

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV)

Alan Sguigna

April 23, 2013
1:57 pm

Back a few years ago, engineers used expensive high-end oscilloscopes to perform signal integrity validation (SIV) on their designs, and considered that adequate in determining the success of a design. But with today’s products, process and parameter variations occur that require system marginality validation (SMV) to be done by less expensive software-based tools, to determine if a design is ready for high volume production.

Structural Defects on High-Speed Serial I/O – Part 3

Alan Sguigna

March 31, 2013
1:51 pm

In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.

Adaptive Equalization and Power Consumption

Alan Sguigna

March 10, 2013
10:25 am

Poorly tuned adaptive equalization will cause systems to gulp power, instead of sipping it. What’s the technology behind this?

Structural Defects on High-Speed Serial I/O

Alan Sguigna

March 2, 2013
4:13 pm

Shorts and open circuits on high-speed serdes buses, such as PCI Express, may have subtle and difficult-to-diagnose effects on system performance. In other words, you might not know about them until customers start complaining and you get warranty returns. What kind of effects are these, and how are they prevented?

DDR4, Signal Integrity, and Power Integrity

Alan Sguigna

February 24, 2013
2:53 pm

One of the biggest design challenges today revolves around maintaining signal integrity in the presence of power and ground rail fluctuations due to simultaneously switching signals. This is particularly true for DDR4 memory.

Signal Integrity Margins of different DIMM Suppliers

Alan Sguigna

February 9, 2013
4:05 pm

Not all memories are created equal. Some DIMM suppliers’ cards have margins that are better than others. And of course, the better the margins, the better the performance of the system, and the fewer blue screens.

How to avoid poor serdes performance caused by circuit board manufacturing variances

Eric Johnson

February 8, 2013
8:24 am

Category: Intel® IBIST

Boundary-Scan Testing of PCI Express

Defects on High-Speed Memory – Part 2

SIV versus SMV – Part 2

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV)

Structural Defects on High-Speed Serial I/O – Part 3

Adaptive Equalization and Power Consumption

Structural Defects on High-Speed Serial I/O

DDR4, Signal Integrity, and Power Integrity

Signal Integrity Margins of different DIMM Suppliers

How to avoid poor serdes performance caused by circuit board manufacturing variances

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