Non-intrusive Board Test (NBT) Archives | Page 2 of 7

JTAG Boundary-Scan Test for the Intel Innovation Engine

Alan Sguigna

September 13, 2015
3:23 pm

As described in earlier blogs, the new Intel Innovation Engine (IE) makes an ideal host for validation, debug, trace and test applications on Intel platforms. This article details the implementation of a JTAG execution engine on the IE for the purposes of printed circuit board structural and functional testing.

Embedded Boundary-Scan Test

Alan Sguigna

August 2, 2015
6:09 pm

Boundary-scan test is used commonly on manufacturing lines with a “benchtop” tester, complete with cables, fixturing, hardware probes, and so on. What are the pros and cons of embedding this technology in-situ?

A new era and new insight – Real Insight

Glenn Woppman

July 13, 2015
1:21 pm

Mixing Embedded eTAPs | 1149.1, IJTAG, Software Debug

Adam Ley

April 7, 2015
4:13 pm

JTAG Diagnostics for Intel® QPI Structural Defects

Kent Zetterberg

December 16, 2014
9:22 am

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Glenn Woppman

December 9, 2014
11:30 am

Memory Training, Testing, and Margining

Alan Sguigna

November 2, 2014
3:38 pm

What happens during DDR memory training/initialization, and how does it differ from what is needed for manufacturing testing or system marginality validation?

JTAG | one TAP, many non-intrusive apps

Adam Ley

September 9, 2014
12:42 pm

The origins of JTAG are inextricably bound up with boundary scan. Yet, it provides many capabilities to many purposes. Often, as part of a point tool, whether for debug, programming, test or validation, it takes on just one capability. But, no matter the purpose, as the thread common to all, the standard Test Access Port (TAP) opens the way for many applications. In the test domain, several of these unite under the banner Non-intrusive Board Test (NBT).

DDR Testing using Spoofed Memory Reference Code – Part 2

Alan Sguigna

July 20, 2014
3:42 pm

In Part 1 of this blog, we discussed some of the limitations of ICT, boundary-scan, and conventional functional test for testing memories. This Part 2 reviews methodologies that overcome these constraints.

DDR Testing using Spoofed Memory Reference Code – Part 1

Alan Sguigna

July 13, 2014
2:55 pm

Off-the-shelf memory initialization routines typically do not provide the needed diagnostic resolution if a structural failure causes the system to “blue screen”. How can test engineers overcome this?

Category: Non-intrusive Board Test (NBT)

JTAG Boundary-Scan Test for the Intel Innovation Engine

Embedded Boundary-Scan Test

A new era and new insight – Real Insight

Mixing Embedded eTAPs | 1149.1, IJTAG, Software Debug

JTAG Diagnostics for Intel® QPI Structural Defects

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Memory Training, Testing, and Margining

JTAG | one TAP, many non-intrusive apps

DDR Testing using Spoofed Memory Reference Code – Part 2

DDR Testing using Spoofed Memory Reference Code – Part 1

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