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Category: Software Debug and Trace – Intel

Coding to the SED API: Part 1

Picture of Alan Sguigna
Alan Sguigna
In my UEFI Forum webinar, I demonstrated a utility function for stressing PCI Express ports at-scale using JTAG. Let’s walk through the source code and see how it works under the hood.

Debugging Intel CATERR using Embedded ITP

Picture of Alan Sguigna
Alan Sguigna
In my webinar with the UEFI Forum, I demonstrated some of the utility of using JTAG functionality within BMCs to perform out-of-band debug. This is a tutorial on the coding practices to use the SED API.

PCI Express LTSSM stress using BMC-based Embedded JTAG/ITP

Picture of Alan Sguigna
Alan Sguigna
This past week, I did a webinar in collaboration with the UEFI Forum on JTAG-based UEFI Debug and Trace. This reviewed some of the often-used tools for low-level triage of difficult-to-diagnose, intermittent bugs. Near the end, I demonstrated the usage of technology running directly down on a BMC to perform low-level functions not achievable with firmware or OS-based applications.

More Skylake Server CScripts Explorations

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Alan Sguigna
In Running Intel CScripts on Skylake servers, I gave a brief introduction to the Intel Customer Scripts (CScripts), and showed how to run them with SourcePoint. Today, I do a deeper dive.

The MinnowBoard Chronicles Episode 46: Using the DediProg SF100

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Alan Sguigna
I’ve been working from home for quite some time now, and don’t have access to all the equipment I normally would have at the office. And I’ve wanted to flash the MinnowBoard (and some other boards). So, rather than wait for the coronavirus shelter-in-place to lift, I went out and bought a DediProg SF100 of my own. Here’s my out-of-the-box experience.

Running Intel CScripts on Skylake servers

Picture of Alan Sguigna
Alan Sguigna
As everyone who works with server designs knows, Intel publishes a group of JTAG-based scripts called the Intel Customer Scripts (ICS, or CScripts for short). The CScripts are derived from internal applications that Intel uses for silicon validation, and they are enormously useful for board bring-up and debug. This week, I took a look at them, and ran some with SourcePoint.

Intel Processor Trace and AET

Picture of Alan Sguigna
Alan Sguigna
In my last few blogs, I’ve looked at the use of Intel Trace features for capturing valuable debug information. In particular, Architectural Event Trace (AET) and Management Engine (ME) message trace are very powerful capabilities. This week, we put these trace events in a meaningful code context by correlating them with Intel Processor Trace (IPT).
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