A leading server OEM is using an embedded implementation of Intel In-Target Probe (ITP) to perform at-scale debugging, without plugging in an external emulator. How does this work?
AppliedMicro has announced availability of their X-Gene Server on a Chip, with a 50% reduction in power consumption and operating costs. How do you debug a platform designed with this part?
Let’s say you wanted to debug a CATERR on an Intel x86-based system out in the field. And let’s say that the CATERR only happened in a given datacenter once a week. An embedded implementation of the In-Target Probe (ITP) would help.
Trace resources within chips allow for viewing of executing code and processor events. Intel processors support facilities such as Last Branch Record (LBR), Branch Trace Store (BTS), and Architecture Event Trace (AET). What are these?
Highly Accelerated Life Testing (HALT) and Highly Accelerated Stress Screening (HASS) are often used to detect faults in electronic systems, testing the extremes and determining the outer limits of system margins. All hardware components and systems will eventually fail under environmental stress. But can this technique be used to improve software reliability as well?
