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Category: Software Debug and Trace

The UP Squared Chronicles Episode 3: Intel Processor Trace

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Alan Sguigna
Wow! It has been a while. I wrote Episode 2 of my open-source explorations into the AAEON Intel Apollo Lake-based Up Squared board back on June 7th. In that episode, I gave directions on how to build the UEFI debug image for the board, complete with source/symbols for consumption by JTAG debuggers like SourcePoint. In this episode, I show source-level debug with SourcePoint, and take advantage of Intel Processor Trace on the board.

Coding to the SED API: Part 4

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Alan Sguigna
In Part 3 of this series, we did a code review of “ltloop”, a utility firmware application that uses the BMC to do out-of-band stress tests of PCI Express ports. In this article, we begin to examine a more general-purpose application that uses JTAG to extract register, memory and IO contents of the target. This On-Target Diagnostic (OTD), called “libtest”, is used by ASSET to test the functionality of run-control on new targets.

Coding to the SED API: Part 3

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Alan Sguigna
In the last article on this topic, we did a dive into the main routine of the lt_loop JTAG-based On-Target Diagnostic, seeing the overall flow of the program. In this article, we’ll look at the routine that does the heavy lifting for retraining the PCI Express link and checking for errors.

Coding to the SED API: Part 2

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Alan Sguigna
In my previous blog, I did a walkthrough of the source code for main() within the ltloop JTAG-based on-target diagnostic. This article covers main() in more detail, and provides insight into some of the operations of the utility functions and data structures.

Coding to the SED API: Part 1

Picture of Alan Sguigna
Alan Sguigna
In my UEFI Forum webinar, I demonstrated a utility function for stressing PCI Express ports at-scale using JTAG. Let’s walk through the source code and see how it works under the hood.

Debugging Intel CATERR using Embedded ITP

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Alan Sguigna
In my webinar with the UEFI Forum, I demonstrated some of the utility of using JTAG functionality within BMCs to perform out-of-band debug. This is a tutorial on the coding practices to use the SED API.

PCI Express LTSSM stress using BMC-based Embedded JTAG/ITP

Picture of Alan Sguigna
Alan Sguigna
This past week, I did a webinar in collaboration with the UEFI Forum on JTAG-based UEFI Debug and Trace. This reviewed some of the often-used tools for low-level triage of difficult-to-diagnose, intermittent bugs. Near the end, I demonstrated the usage of technology running directly down on a BMC to perform low-level functions not achievable with firmware or OS-based applications.

More Skylake Server CScripts Explorations

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Alan Sguigna
In Running Intel CScripts on Skylake servers, I gave a brief introduction to the Intel Customer Scripts (CScripts), and showed how to run them with SourcePoint. Today, I do a deeper dive.
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