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Coding to the SED API: Part 4

Alan Sguigna

October 18, 2020
4:52 pm

In Part 3 of this series, we did a code review of “ltloop”, a utility firmware application that uses the BMC to do out-of-band stress tests of PCI Express ports. In this article, we begin to examine a more general-purpose application that uses JTAG to extract register, memory and IO contents of the target. This On-Target Diagnostic (OTD), called “libtest”, is used by ASSET to test the functionality of run-control on new targets.

Coding to the SED API: Part 3

Alan Sguigna

September 20, 2020
7:56 pm

In the last article on this topic, we did a dive into the main routine of the lt_loop JTAG-based On-Target Diagnostic, seeing the overall flow of the program. In this article, we’ll look at the routine that does the heavy lifting for retraining the PCI Express link and checking for errors.

Coding to the SED API: Part 2

Alan Sguigna

September 7, 2020
3:35 pm

In my previous blog, I did a walkthrough of the source code for main() within the ltloop JTAG-based on-target diagnostic. This article covers main() in more detail, and provides insight into some of the operations of the utility functions and data structures.

Coding to the SED API: Part 1

Alan Sguigna

August 30, 2020
4:11 pm

In my UEFI Forum webinar, I demonstrated a utility function for stressing PCI Express ports at-scale using JTAG. Let’s walk through the source code and see how it works under the hood.

Debugging Intel CATERR using Embedded ITP

Alan Sguigna

July 26, 2020
8:44 pm

In my webinar with the UEFI Forum, I demonstrated some of the utility of using JTAG functionality within BMCs to perform out-of-band debug. This is a tutorial on the coding practices to use the SED API.

PCI Express LTSSM stress using BMC-based Embedded JTAG/ITP

Alan Sguigna

July 19, 2020
4:27 pm

This past week, I did a webinar in collaboration with the UEFI Forum on JTAG-based UEFI Debug and Trace. This reviewed some of the often-used tools for low-level triage of difficult-to-diagnose, intermittent bugs. Near the end, I demonstrated the usage of technology running directly down on a BMC to perform low-level functions not achievable with firmware or OS-based applications.

ISO 9001: What is it and why is it so important to ASSET InterTech?

Heidi Richards

July 7, 2020
3:01 pm

You may be asking yourself, what is ISO 9001 and why is it so important to ASSET InterTech?

Enhancements to JTAG-based test and device programming

Larry Osborn

June 25, 2020
9:35 am

Watching a product mature is a great experience. Working with ScanWorks for over 15 years has provided a unique opportunity to assist in the maturation process from a point solution to that of a platform. Most of my experience has been in taking business opportunities and developing other tools that start out addressing a customer or niche market needs. These adventures almost always end in a point tool. After product deployment and working with more and more customers, the product evolves to the point but, too often there it is still missing a little something. Then looking at the products in-house you find the missing piece. By extending an interface here and there, you begin to see how to integrate tools together within the architecture and that provide a much better problem-solving solution and better user experience. ScanWorks had evolved to a world-class boundary scan test tool. To make it better, it needed to evolve into a platform where other tools could interface using the same target connection infrastructure, JTAG. Here are examples of two such point tools that are being integrated within ScanWorks. These and other features make ScanWorks a world-class tool and platform by enabling functional test and FPGA embedded instruments.

Webinar on JTAG-based UEFI Debug & Trace

Alan Sguigna

June 24, 2020
2:23 pm

ASSET will be presenting JTAG-based UEFI Debug & Trace at the UEFI Forum’s 2020 Virtual Plugfest, on July 14th.

Test Generation for “Chiplet”-based, Multi-die Devices Is Now Possible with ScanWorks

Michael Johnson

June 24, 2020
1:28 pm

Since its inception, ScanWorks has provided board-level shorts and opens testing of interconnects between Boundary-Scan devices through use of its Automatic Test Pattern Generation (ATPG) feature. ScanWorks ATPG creates the patterns necessary for shorts and opens testing based on the board topology (i.e. connections between devices) and the Boundary-Scan Cell types on the I/O pins within each device. With recent enhancements, ScanWorks can now generate patterns that can be applied by chip-level automatic test equipment (ATE) to test for shorts and opens in the interconnections between silicon “chiplets” in multi-die devices.

Coding to the SED API: Part 4

Coding to the SED API: Part 3

Coding to the SED API: Part 2

Coding to the SED API: Part 1

Debugging Intel CATERR using Embedded ITP

PCI Express LTSSM stress using BMC-based Embedded JTAG/ITP

ISO 9001: What is it and why is it so important to ASSET InterTech?

Enhancements to JTAG-based test and device programming

Webinar on JTAG-based UEFI Debug & Trace

Test Generation for “Chiplet”-based, Multi-die Devices Is Now Possible with ScanWorks

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