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DDR Crosstalk Analysis using Margining Technologies

Alan Sguigna

June 22, 2014
8:02 pm

In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?

PCI Express 4.0, Retimers, and Trace Length

Alan Sguigna

June 15, 2014
4:39 pm

At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?

Shorten Firmware Development Time, Use the Right Tools

Larry A. Traylor

June 13, 2014
4:19 pm

SPI Flash JTAG Programming Using a Xilinx Spartan® FPGA

Kent Zetterberg

June 10, 2014
4:10 pm

Bit Error Rate of Intel QuickPath Interconnect – Part 2

Alan Sguigna

June 8, 2014
4:34 pm

In a previous blog, we touched on some of the key attributes of Intel QuickPath Interconnect versus PCI Express Gen3, to explain why the acceptable bit error rate threshold of Intel QPI is two orders of magnitude lower. This article elaborates on how some of the key design features of QPI contribute to this more stringent requirement.

Common SATA Signal Integrity Issues

Alan Sguigna

June 1, 2014
1:43 pm

Serial ATA (SATA)-based systems come in a wide range of topologies and trace/cable lengths. This presents signal integrity challenges due to signal loss, reflection and crosstalk; causing SATA device detection problems, lack of interoperability, slower performance, and increased radio frequency interference. What are the main issues, and how do designers mitigate them?

Embedded IJTAG | P1687 BIST | DFTMAX Synopsys | ScanWorks

Alan Sguigna

May 22, 2014
2:23 pm

The most common questions we field about the IEEE P1687 IJTAG (Internal JTAG) standard for embedded instrumentation are: “Is anyone using P1687? Does it have real and practical applications?” The answer to these questions is an emphatic YES!

Freescale EzPort Programmer with JTAG | FPGA

Kent Zetterberg

May 8, 2014
5:05 am

System Marginality Validation DDR Memory and Serial IO

Alan Sguigna

May 1, 2014
10:32 am

Bit Error Rate of Intel QuickPath Interconnect – Part 1

Alan Sguigna

April 27, 2014
4:02 pm

The required Bit Error Rate (BER) of Intel® QuickPath Interconnect (QPI) is 1 error in 10E14 bits. The BER threshold of PCI Express is 1 error in 10E12 bits. What might account for the two orders of magnitude difference?

DDR Crosstalk Analysis using Margining Technologies

PCI Express 4.0, Retimers, and Trace Length

Shorten Firmware Development Time, Use the Right Tools

SPI Flash JTAG Programming Using a Xilinx Spartan® FPGA

Bit Error Rate of Intel QuickPath Interconnect – Part 2

Common SATA Signal Integrity Issues

Embedded IJTAG | P1687 BIST | DFTMAX Synopsys | ScanWorks

Freescale EzPort Programmer with JTAG | FPGA

System Marginality Validation DDR Memory and Serial IO

Bit Error Rate of Intel QuickPath Interconnect – Part 1

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