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Bit Error Rate of Intel QuickPath Interconnect – Part 1

Alan Sguigna

April 27, 2014
4:02 pm

The required Bit Error Rate (BER) of Intel® QuickPath Interconnect (QPI) is 1 error in 10E14 bits. The BER threshold of PCI Express is 1 error in 10E12 bits. What might account for the two orders of magnitude difference?

DDR4 Memory Timing Margining

Alan Sguigna

April 20, 2014
4:54 pm

Last week we reviewed how voltage margining was performed on DDR3 and DDR4-based systems. How is timing margining done?

Fast Flash Parallel In-System Programming | ISP | JTAG

Kent Zetterberg

April 10, 2014
12:58 pm

DDR4 vs DDR3 Memory Voltage Margining

Alan Sguigna

April 7, 2014
8:38 pm

DDR4 SDRAM brings lower voltage and faster speeds. What are the implications for system marginality validation (SMV)?

What is Surprise Link Down (SLD)?

Alan Sguigna

March 30, 2014
3:42 pm

PCI-SIG specifies a bit error rate (BER) threshold of 1E-12 or better for PCI Express 3.0. What might cause this threshold to be exceeded, and what happens if it is?

The Statistical Basis of System Marginality Validation (SMV)

Alan Sguigna

March 16, 2014
4:48 pm

Determining the margins of a system requires taking a statistically large-enough data collection sample size to achieve a meaningful result. The sample size takes into account variances due to silicon process, temperature, voltage, finite test time, and a number of other factors. What is the math behind this?

Serial Port Functional Test with FPGA UART IP and JTAG

Kent Zetterberg

March 11, 2014
7:00 am

What is Board Bring-Up – Part 2

Alan Sguigna

March 9, 2014
4:09 pm

We know that the board bring-up process can be extremely challenging on today’s complex, high-speed designs. How do we get the iterative validation, test and debug steps off of the critical path of new product introduction?

Structural Defects on Intel QuickPath Interconnect – Part 2

Alan Sguigna

March 2, 2014
1:24 pm

Suppose there’s a hidden short-circuit on an Intel QPI net under the CPU socket – what’s the customer going to see?

Boundary-Scan Testing of Memories, and output2 Cells

Alan Sguigna

February 24, 2014
7:20 am

A customer found that their older ICT-based boundary-scan test tool was creating bus contention during memory testing. Let the buyer beware!

Bit Error Rate of Intel QuickPath Interconnect – Part 1

DDR4 Memory Timing Margining

Fast Flash Parallel In-System Programming | ISP | JTAG

DDR4 vs DDR3 Memory Voltage Margining

What is Surprise Link Down (SLD)?

The Statistical Basis of System Marginality Validation (SMV)

Serial Port Functional Test with FPGA UART IP and JTAG

What is Board Bring-Up – Part 2

Structural Defects on Intel QuickPath Interconnect – Part 2

Boundary-Scan Testing of Memories, and output2 Cells

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