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A customer shared some empirical results from boundary-scan testing of the Intel QuickPath Interconnect (QPI) nets on their design. These nets cannot be covered using In-Circuit Test (ICT), and some short-circuit and open-circuit defects defy detection using conventional functional test. What did they find?
Boundary scan is known to be quite slow to program large flash devices. But, with a new approach using SPI Master IP within an FPGA, flash programming time can be decreased by a factor of 15 or more.
Letโ€™s say you wanted to debug a CATERR on an Intel x86-based system out in the field. And letโ€™s say that the CATERR only happened in a given datacenter once a week. An embedded implementation of the In-Target Probe (ITP) would help.
A Case Study showed that 50% of circuit boards that tested as โ€œdeadโ€ in manufacturing production actually have defects on their memory buses. What categories of memory interconnect defects cause a dead board?
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