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Structural Defects on Intel QuickPath Interconnect – Part 2

Alan Sguigna

March 2, 2014
1:24 pm

Suppose there’s a hidden short-circuit on an Intel QPI net under the CPU socket – what’s the customer going to see?

Boundary-Scan Testing of Memories, and output2 Cells

Alan Sguigna

February 24, 2014
7:20 am

A customer found that their older ICT-based boundary-scan test tool was creating bus contention during memory testing. Let the buyer beware!

Greater visibility into ThreadX resources and multithreaded code execution

Larry Osborn

February 20, 2014
1:27 pm

Structural Defects on Intel QuickPath Interconnect

Alan Sguigna

February 16, 2014
11:37 am

A customer shared some empirical results from boundary-scan testing of the Intel QuickPath Interconnect (QPI) nets on their design. These nets cannot be covered using In-Circuit Test (ICT), and some short-circuit and open-circuit defects defy detection using conventional functional test. What did they find?

Fast SPI Flash Programming

Alan Sguigna

February 9, 2014
5:06 pm

Boundary scan is known to be quite slow to program large flash devices. But, with a new approach using SPI Master IP within an FPGA, flash programming time can be decreased by a factor of 15 or more.

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV) – Part 3

Alan Sguigna

February 2, 2014
5:26 pm

In previous blogs, we contrasted the use of oscilloscopes to perform signal integrity validation (SIV) against silicon embedded instruments for system marginality validation (SMV). Why is SMV superior?

Debug and Trace using ARM® System Trace Macrocell (STM)

Larry Osborn

January 21, 2014
2:06 pm

Debugging CATERR in field systems

Alan Sguigna

January 18, 2014
4:46 pm

Let’s say you wanted to debug a CATERR on an Intel x86-based system out in the field. And let’s say that the CATERR only happened in a given datacenter once a week. An embedded implementation of the In-Target Probe (ITP) would help.

IJTAG explained in IEEE’s Design & Test magazine

Al Crouch

January 9, 2014
4:58 pm

Tutorial | Board Test of DDR3|DDR4 Memory and Serial IO

Alan Sguigna

December 10, 2013
5:02 pm

Structural Defects on Intel QuickPath Interconnect – Part 2

Boundary-Scan Testing of Memories, and output2 Cells

Greater visibility into ThreadX resources and multithreaded code execution

Structural Defects on Intel QuickPath Interconnect

Fast SPI Flash Programming

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV) – Part 3

Debug and Trace using ARM® System Trace Macrocell (STM)

Debugging CATERR in field systems

IJTAG explained in IEEE’s Design & Test magazine

Tutorial | Board Test of DDR3|DDR4 Memory and Serial IO

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