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What are Intel LBR, BTS, and AET?

Alan Sguigna

November 24, 2013
3:30 pm

Trace resources within chips allow for viewing of executing code and processor events. Intel processors support facilities such as Last Branch Record (LBR), Branch Trace Store (BTS), and Architecture Event Trace (AET). What are these?

Software Debug in Environmental Chambers

Alan Sguigna

November 10, 2013
4:28 pm

Highly Accelerated Life Testing (HALT) and Highly Accelerated Stress Screening (HASS) are often used to detect faults in electronic systems, testing the extremes and determining the outer limits of system margins. All hardware components and systems will eventually fail under environmental stress. But can this technique be used to improve software reliability as well?

Testing System Clocks with an FPGA
and JTAG | Boundary Scan

Kent Zetterberg

October 1, 2013
1:34 pm

Will BIST Kill T&M?

Alan Sguigna

September 29, 2013
5:14 pm

To quote Ransom Stephens in the DesignCon Community Blog, “BIST (Built-In System Test), is an acronym that would keep executives at test-and-measurement companies awake at night, if they knew what it meant.” What’s he talking about?

At-speed SPI Flash/EEPROM Programming using FPGA and JTAG

Kent Zetterberg

September 3, 2013
5:00 pm

Silicon Aging and Signal Integrity

Alan Sguigna

August 25, 2013
4:40 pm

Fruit rots. Tires wear out. And silicon ages, too. Let’s look at the degradation process and its effects on chip signal integrity and performance.

Faster Firmware Debug with Intel Embedded Trace Tools

Larry Osborn

August 14, 2013
9:50 am

Testing DDR3 Memory with Boundary Scan/JTAG | eBook

Johan Renberg

July 31, 2013
4:40 pm

Boundary-Scan Testing of DDR3 and DDR4 Memory

Alan Sguigna

July 13, 2013
4:52 pm

In the blog Boundary-Scan Testing of PCI Express, we examined how JTAG can be used to detect structural defects on high-speed serial I/O. Now let’s review the situation for DDR3 and DDR4 memory.

ASSET and Arium merge – It’s all about visibility! Your visibility!

Glenn Woppman

July 9, 2013
10:48 am

What are Intel LBR, BTS, and AET?

Software Debug in Environmental Chambers

Testing System Clocks with an FPGA
and JTAG | Boundary Scan

Will BIST Kill T&M?

At-speed SPI Flash/EEPROM Programming using FPGA and JTAG

Silicon Aging and Signal Integrity

Faster Firmware Debug with Intel Embedded Trace Tools

Testing DDR3 Memory with Boundary Scan/JTAG | eBook

Boundary-Scan Testing of DDR3 and DDR4 Memory

ASSET and Arium merge – It’s all about visibility! Your visibility!

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