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Structural Defects on Intel QuickPath Interconnect

Alan Sguigna

February 16, 2014
11:37 am

A customer shared some empirical results from boundary-scan testing of the Intel QuickPath Interconnect (QPI) nets on their design. These nets cannot be covered using In-Circuit Test (ICT), and some short-circuit and open-circuit defects defy detection using conventional functional test. What did they find?

Fast SPI Flash Programming

Alan Sguigna

February 9, 2014
5:06 pm

Boundary scan is known to be quite slow to program large flash devices. But, with a new approach using SPI Master IP within an FPGA, flash programming time can be decreased by a factor of 15 or more.

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV) – Part 3

Alan Sguigna

February 2, 2014
5:26 pm

In previous blogs, we contrasted the use of oscilloscopes to perform signal integrity validation (SIV) against silicon embedded instruments for system marginality validation (SMV). Why is SMV superior?

Debug and Trace using ARM® System Trace Macrocell (STM)

Larry Osborn

January 21, 2014
2:06 pm

Debugging CATERR in field systems

Alan Sguigna

January 18, 2014
4:46 pm

Let’s say you wanted to debug a CATERR on an Intel x86-based system out in the field. And let’s say that the CATERR only happened in a given datacenter once a week. An embedded implementation of the In-Target Probe (ITP) would help.

IJTAG explained in IEEE’s Design & Test magazine

Al Crouch

January 9, 2014
4:58 pm

Tutorial | Board Test of DDR3|DDR4 Memory and Serial IO

Alan Sguigna

December 10, 2013
5:02 pm

Debugging Dead Boards in Production

Alan Sguigna

December 7, 2013
3:04 pm

A Case Study showed that 50% of circuit boards that tested as “dead” in manufacturing production actually have defects on their memory buses. What categories of memory interconnect defects cause a dead board?

System Test | Gateway Scan Bridge | Boundary Scan JTAG

Kent Zetterberg

December 5, 2013
12:56 pm

What are Intel LBR, BTS, and AET?

Alan Sguigna

November 24, 2013
3:30 pm

Trace resources within chips allow for viewing of executing code and processor events. Intel processors support facilities such as Last Branch Record (LBR), Branch Trace Store (BTS), and Architecture Event Trace (AET). What are these?

Structural Defects on Intel QuickPath Interconnect

Fast SPI Flash Programming

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV) – Part 3

Debug and Trace using ARM® System Trace Macrocell (STM)

Debugging CATERR in field systems

IJTAG explained in IEEE’s Design & Test magazine

Tutorial | Board Test of DDR3|DDR4 Memory and Serial IO

Debugging Dead Boards in Production

System Test | Gateway Scan Bridge | Boundary Scan JTAG

What are Intel LBR, BTS, and AET?

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