Blog

Debugging Dead Boards in Production

Alan Sguigna

December 7, 2013
3:04 pm

A Case Study showed that 50% of circuit boards that tested as “dead” in manufacturing production actually have defects on their memory buses. What categories of memory interconnect defects cause a dead board?

System Test | Gateway Scan Bridge | Boundary Scan JTAG

Kent Zetterberg

December 5, 2013
12:56 pm

What are Intel LBR, BTS, and AET?

Alan Sguigna

November 24, 2013
3:30 pm

Trace resources within chips allow for viewing of executing code and processor events. Intel processors support facilities such as Last Branch Record (LBR), Branch Trace Store (BTS), and Architecture Event Trace (AET). What are these?

Software Debug in Environmental Chambers

Alan Sguigna

November 10, 2013
4:28 pm

Highly Accelerated Life Testing (HALT) and Highly Accelerated Stress Screening (HASS) are often used to detect faults in electronic systems, testing the extremes and determining the outer limits of system margins. All hardware components and systems will eventually fail under environmental stress. But can this technique be used to improve software reliability as well?

Testing System Clocks with an FPGA
and JTAG | Boundary Scan

Kent Zetterberg

October 1, 2013
1:34 pm

Will BIST Kill T&M?

Alan Sguigna

September 29, 2013
5:14 pm

To quote Ransom Stephens in the DesignCon Community Blog, “BIST (Built-In System Test), is an acronym that would keep executives at test-and-measurement companies awake at night, if they knew what it meant.” What’s he talking about?