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How to avoid poor serdes performance caused by circuit board manufacturing variances

Eric Johnson

February 8, 2013
8:24 am

IEEE P1687 Internal JTAG (IJTAG) taps into embedded instrumentation

Al Crouch

January 29, 2013
9:40 am

The Intel Cougar Point SATA Bug

Alan Sguigna

January 26, 2013
1:48 pm

In early 2011, Intel discovered a design issue on their Cougar Point chipset, and took an approximately $700 million charge against earnings to repair and replace affected parts and systems. What may have been the root cause of this, and how may it have been prevented?

Margins (Eye Diagrams) follow the Silicon – Part 2

Alan Sguigna

January 20, 2013
10:17 am

In my previous blog I covered at a high level why system signal integrity is highly dependent upon the silicon. Let’s dive into this a little deeper by first looking at wafer and die manufacturing variances.

Signal Integrity testing with CRCs versus pattern generation and capture

Alan Sguigna

January 9, 2013
4:45 pm

I was asked recently whether engineers could just check the CRC error counts coming from the Operating System to ensure they had good signal integrity and operating margins. After all, a CRC checks for bit errors, right? Here’s why this is not good enough:

Diminishing ICT Test Coverage

Alan Sguigna

December 31, 2012
4:28 pm

Our chief technologist of non-intrusive board test, Adam Ley, recently published an e-Book on solving the problem of diminishing test coverage from In-Circuit Test (ICT). What’s the key take-away from this publication?

e-Book: Solving the Problem of Diminishing Test Coverage from In-Circuit Test (ICT)

Arden Bjerkeli

December 18, 2012
2:12 pm

How to eliminate throw-away code

Larry Osborn

December 11, 2012
10:18 am

Margins (Eye Diagrams) follow the Silicon

Alan Sguigna

December 9, 2012
8:07 pm

We know from empirical evidence that a system’s operating margins are as sensitive to the chips on the board, as they are to the board’s design and manufacturing process itself. Why is this so?

Adaptive Equalization – Part 2

Alan Sguigna

December 2, 2012
11:56 am

In a previous blog, I described how fixed and adaptive equalization techniques are used within chips to ensure signal integrity even in adverse system conditions. Why is it important to tune these parameters within a chip?

How to avoid poor serdes performance caused by circuit board manufacturing variances

IEEE P1687 Internal JTAG (IJTAG) taps into embedded instrumentation

The Intel Cougar Point SATA Bug

Margins (Eye Diagrams) follow the Silicon – Part 2

Signal Integrity testing with CRCs versus pattern generation and capture

Diminishing ICT Test Coverage

e-Book: Solving the Problem of Diminishing Test Coverage from In-Circuit Test (ICT)

How to eliminate throw-away code

Margins (Eye Diagrams) follow the Silicon

Adaptive Equalization – Part 2

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