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Structural Defects on High-Speed Serial I/O

Alan Sguigna

March 2, 2013
4:13 pm

Shorts and open circuits on high-speed serdes buses, such as PCI Express, may have subtle and difficult-to-diagnose effects on system performance. In other words, you might not know about them until customers start complaining and you get warranty returns. What kind of effects are these, and how are they prevented?

Cache-as-RAM for board bring-up of non-booting circuit boards

Larry Osborn

February 25, 2013
2:25 pm

DDR4, Signal Integrity, and Power Integrity

Alan Sguigna

February 24, 2013
2:53 pm

One of the biggest design challenges today revolves around maintaining signal integrity in the presence of power and ground rail fluctuations due to simultaneously switching signals. This is particularly true for DDR4 memory.

Signal Integrity Margins of different DIMM Suppliers

Alan Sguigna

February 9, 2013
4:05 pm

Not all memories are created equal. Some DIMM suppliers’ cards have margins that are better than others. And of course, the better the margins, the better the performance of the system, and the fewer blue screens.

How to avoid poor serdes performance caused by circuit board manufacturing variances

Eric Johnson

February 8, 2013
8:24 am

IEEE P1687 Internal JTAG (IJTAG) taps into embedded instrumentation

Al Crouch

January 29, 2013
9:40 am

The Intel Cougar Point SATA Bug

Alan Sguigna

January 26, 2013
1:48 pm

In early 2011, Intel discovered a design issue on their Cougar Point chipset, and took an approximately $700 million charge against earnings to repair and replace affected parts and systems. What may have been the root cause of this, and how may it have been prevented?

Margins (Eye Diagrams) follow the Silicon – Part 2

Alan Sguigna

January 20, 2013
10:17 am

In my previous blog I covered at a high level why system signal integrity is highly dependent upon the silicon. Let’s dive into this a little deeper by first looking at wafer and die manufacturing variances.

Signal Integrity testing with CRCs versus pattern generation and capture

Alan Sguigna

January 9, 2013
4:45 pm

I was asked recently whether engineers could just check the CRC error counts coming from the Operating System to ensure they had good signal integrity and operating margins. After all, a CRC checks for bit errors, right? Here’s why this is not good enough:

Diminishing ICT Test Coverage

Alan Sguigna

December 31, 2012
4:28 pm

Our chief technologist of non-intrusive board test, Adam Ley, recently published an e-Book on solving the problem of diminishing test coverage from In-Circuit Test (ICT). What’s the key take-away from this publication?

Structural Defects on High-Speed Serial I/O

Cache-as-RAM for board bring-up of non-booting circuit boards

DDR4, Signal Integrity, and Power Integrity

Signal Integrity Margins of different DIMM Suppliers

How to avoid poor serdes performance caused by circuit board manufacturing variances

IEEE P1687 Internal JTAG (IJTAG) taps into embedded instrumentation

The Intel Cougar Point SATA Bug

Margins (Eye Diagrams) follow the Silicon – Part 2

Signal Integrity testing with CRCs versus pattern generation and capture

Diminishing ICT Test Coverage

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